Hello there,
Please see below for details.
General Details:
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Hardware Platform : Ambiq SoC Apollo4 Blue Plus (Cortex M4F + M0).
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FreeRTOS version : v10.1.1
Firmware Description:
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Thread 1 to handles communication. Intends to send the data after post processing completed by thread 2.
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Thread 2 to process data received from a hardware peripheral.
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On the hardware platform we have configured a peripheral that provides data using a DMA. We expect to receive an interrupt at every ~85mS from DMA controller. In this ISR we use the below code to inform thread 2 to process the data.
vTaskNotifyGiveFromISR(Thread2Handle, &xHigherPriorityTaskWoken);
if(xHigherPriorityTaskWoken)
{
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}
- Thread 2 is blocked until it receives a notification as shown below.
if(ulTaskNotifyTake(pdTRUE, portMAX_DELAY) != pdFALSE)
{
// do post processing of the data
}
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Following are the priorities of the threads. Thread 1 priority is 2. Thread 2 priority is 3. Thread 1 wakes up nomially at ~500mS spends above 100uS to run few instructions.
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DMA interrupt priority is set to 4.
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RTOS related interrupt nesting definitions are below. Provided by Manufacturer (Ambiq)
#define configKERNEL_INTERRUPT_PRIORITY (0x7 << 5)
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0x4 << 5)
#define NVIC_configKERNEL_INTERRUPT_PRIORITY (0x7)
#define NVIC_configMAX_SYSCALL_INTERRUPT_PRIORITY (0x4)
Problem Statement
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Both threads are spawned and if task notification is used then the interrupt rate changes from ~85mS to ~91mS. This leads to unexpected result.
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As a test, the communication hardware peripheral handled by thread 1 was turned off and the issues seems to be fixed meaning the interrupt rate is 85mS. However, this is not a feasible solution since we need to ship this data using Thread 1.
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As another test, the communication hardware peripheral handled by thread 1 is turned ON and after 5 seconds thread 1 is suspended and thread 2 is resumed. Interrupt rate is as expected at ~85mS.
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I have also tried to increase the priority of configMAX_SYSCALL_INTERRUPT_PRIORITY to (0x5 << 5) so the peripheral interrupt priority is lower than syscall_interrupt prirority. But the issue still exists.
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At this point I am contemplating if the issue is due to the OS or due to the hardware component used for communication in thread 1 is somehow messing the DMA interrupt rate. I am not sure and hence looking to get some suggestions from the community.
Thank you.