What do you mean “not fully align with the code?”
Let me clarify. We using the code from https://github.com/FreeRTOS/FreeRTOS-Kernel.
What I talked above is from folder portable/GCC/ARM_CA53_64_BIT. It is a portable part for Cortex A53 core with AARCH64
In the code:
taskENTER_CRITICAL: it just mask IRQ, it won’t affect SVC call (right?)
portYIELD_WITHIN_API==>svc 0 ==> Triger exception==>FreeRTOS_SWI_Handler is called for task switch (it is my understanding)
If the SVC would indeed immediately and unconditionally invoke the handler with disregard to priorities and interrupt mask
This is my understanding.
BTW, what is this #ifdef GUEST all about?
GEUST means it is running in EL1. For our case, GUEST is true/defined
This is a similar Can a Switch to another task occur between the call “taskENTER_CRITICAL” and “taskEXIT_CRITICAL”? with comments in this thread:
but such as on CA9, the volunteer yield operation is done through “svc” call, which would step into svc flow directely and do the swich at once, i did not see any condition would block this switch,
it seems the swith would happed and success on CA9 port., which meas voluteer yiled could be done in “taskENTER_xxxx” and “taskEXIT_xxxx” region.