Tickless Idle on CC3200

ammaree wrote on Friday, January 08, 2016:

In my process to improve on power consumption on the CC3200 using FreeRTOS Tickless idle I came across the problem with Cystic being a 24 bit timer.

Using a 1mS tick at 80 Mhz this resulted in ~200mS max of sleep. On further research I came across the PAOSC option where SysTick can be clocked at 10Mhz thus possibly extending the duration to around 1677mS.

Having had a look at the source code I specifically noticed that the NVIC is configured such as to ensure SysTick runs at the full 80MHz core clock.

My questions are:
Q1: Is there any reason FreeRTOS does not make standard provision for using this alternative clock option?
Q2: Is there anything specific to consider before using this CLKSOURCE=0 option?
Q3: What mechanism would the the simplest and most portable to implement this option?

All help appreciated.

rtel wrote on Friday, January 08, 2016:

The FreeRTOS Cortex-M3/4/4F/7 ports are written to allow any of the defaults to be overridden.

If you look at the top of http://sourceforge.net/p/freertos/code/HEAD/tree/trunk/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c - line 82 - you will see that you can define configSYSTICK_CLOCK_HZ in the FreeRTOSConfig.h header file if your hardware is setup to clock SysTick from a different clock to that which clocks the CPU.

If you look at line 665 you will notice that even the function that sets up the clock used to generate the tick is a weak symbol, so you can override that in the application too.

It is documented on the FreeRTOS website that the SysTick clock is not much use for extra long tickless idling, as it is only 24-bits and too fast. That is why the reference tickless implementations available in the FreeRTOS download use slower clocks. A low power 32-bit 32KHz watch crystal type clock allows you to stay in low power mode for months. [all the tickless implementation stuff can be overridden too]