rtel wrote on Sunday, December 29, 2013:
It is the maximum number of tick periods that can be counted in your timer before the timer overflows. Its value is therefore dependent on the width of the timer’s counter in bits and the timer’s frequency.
In the generic tickless implementation which uses the Cortex-M SysTick timer (which is only 24-bits) then you can see it being calculated as follows:
First work out how many SysTick timer increments are required to generate one tick period by dividing the timer’s frequency specified in Hz by the tick rate specified in Hz:
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
Then see how many times the timer can count the resultant number before the timer overflows - which in this case is how many times ulTimerCountsForOneTick will fit into the SysTick timer’s 24-bit counter register:
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
Therefore, the timer can be used to generate an interrupt xMaximumPossibleSuppressedTicks tick periods into the future because xMaximumPossibleSuppressedTicks * ulTimerCountsForOneTick will fit into the 24-bit number.
You can see then that the SysTick timer is not capable of allowing extended tickless periods because it is limited to only 24-bits and a fast time input. Therefore tickless implementations that are tailored to a specific chips will ideally use a slow clock (32Khz is common) and a 32-bit timer - allowing tickless periods that extend into months rather than fractions of a second.