heinbali01 wrote on Friday, May 20, 2016:
I’m reading a PDF ug0250_v5.
It looks like you can have any alignment for the transmission buffers:
31:0 TBA1 Transmit buffer 1 address
Contains the address of the first data buffer. For the setup frame,
this address must be 32-bit word aligned.
In all other cases, there are no restrictions on buffer alignment.
31:0 TBA2 Transmit buffer 2 address
Contains the address of the second data buffer. There are
no restrictions on buffer alignment.
For reception, a 32-bit alignment seems to be expected:
31:0 RBA1 Receive buffer 1 address
Indicates the length, in bytes, of memory allocated for the
first receive buffer. This number must be 32-bit word aligned.
31:0 RBA2 Receive buffer 2 address
Indicates the length, in bytes, of memory allocated for the second
receive buffer. This number must be 32-bit word aligned.
I’m not sure if I understand your proposal correctly. But I’ll try to sketch some possibilities:
For the RX path, I’m afraid that your EMAC doesn’t accept the +2 byte alignment.
For the TX path, you can pass
pucEthernetBuffer pointers to DMA. After every transmission, there will be a TX-ready interrupt which will wake-up the EMAC task. The task will then release the TX buffers that are transmitted.
There is no need to track association of buffer with NetworkBufferDescriptor_t.
Not sure what you mean here? The pointer to the owner is sometimes needed by the IP task and the application.