/* Set the LR to the task stack. */
asm volatile (
"LDR R0, =pxCurrentTCB \n\t"
"LDR R0, [R0] \n\t"
"LDR LR, [R0] \n\t"
/* The critical nesting depth is the first item on the stack. */
/* Load it into the ulCriticalNesting variable. */
"LDR R0, =ulCriticalNesting \n\t"
"LDMFD LR!, {R1} \n\t"
"STR R1, [R0] \n\t"
/* Get the SPSR from the stack. */
"LDMFD LR!, {R0} \n\t"
"MSR SPSR, R0 \n\t"
/* Restore all system mode registers for the task. */
"LDMFD LR, {R0-R14}^ \n\t"
"NOP \n\t"
/* And return - correcting the offset in the LR to obtain the */
/* correct address. */
"SUBS PC, LR, #4 \n\t"
);
( void ) ulCriticalNesting;
( void ) pxCurrentTCB;
}
Okey i found a SOLUTION I used the startup and linker file from the SAM7X - Eclipse Sample Projekt.
I think the Problem is, that my old startup code did support nested interrupts.
But can someone help me with an explanation what could go wrong if the startupcode supports nested interrupts?
The startup code must either configure the IRQ handler to vector directly to the interrupt handler or vector to a common entry point that contains the context saving code. Examples are provided of both methods. In either case the first code executed after the jump must be the FreeRTOS.org context save code, not any compiler provided intermediary code. This is to ensure that the task finds the stack in exactly the state it expects when exiting an ISR.
The main reason for this is that a task can be placed into the blocked state from a call to Yield at the task level, but start executing again after being moved out of the blocked state within an ISR. In both cases it needs to have the stack popped back into the registers in exactly the same way.
You can implement nesting of interrupts by modifying the code after the saving of the context only. It is unlikely that nesting of interrupts would be required though. See http://www.freertos.org/FAQISR.html#Nest for more info.