Don’t mix up (logical) FreeRTOS task priorities and HW specific interrupt priorities. These are different and independent things.
However, when using FreeRTOS calls in ISRs (the API tagged with FromISR) some constraints come into play due to so called critical sections in the FreeRTOS code and also in application code.
Critical sections are implemented in FreeRTOS by disabling interrupts.
For CPUs like Cortex-M3/4 etc. supporting interrupt priorities only the relevant part of the interrupt priorities are disabled allowing to use interrupts/ISRs at higher priority but without any FreeRTOS API call. These interrupts are never disabled and the corresponding ISRs would provide even harder real-time behavior. In other words there is no jitter invoking the ISR on interrupt caused by (very short) critical sections. Except there are some more of those interrupts with even higher interrupt priority, of course.
Hope it helps a bit
Since Renesas RA family also have a Cortex-M CPU see this related documentation: