Status of floating point register management support on RISC-V port


I am curious what the status is of FPU/floating point register management on the FreeRTOS port to RISC-V. It looks like at one point it was supported, and then removed? Has it even been added back?


Floating point support is not yet added.

Some partner supported forks include floating point.

I’m currently running SiFive’s FreeRTOS-Metal port on a custom SOC based on a SiFive E34 core. Although, I’m looking to pivot from the FreeROTS-Metal port, and use the FreeRTOS-kernel RISC-V port instead, due to SiFive’s seeming lack of maintenance & upkeep for their port (even though theirs does support floating point). Do you plan to add support for floating point in the future?

How easy would it be for you create a PR that adds that floating point support into the upstream version?