kj-lin wrote on Thursday, September 05, 2019:
According to the standard RISC-V calling convention, the stack pointer $sp is always 16-byte aligned.
It seems that FreeRTOS RISC-V port doesn’t meet the requirement because it defines the “portBYTE_ALIGNMENT” value to 8 in portmacro.h file.
In order for $sp 16-byte alignment, should the “portBYTE_ALIGNMENT” definition be changed from 8 to 16?
Or i misunderstand something about the FreeRTOS RISC-V porting ?
rtel wrote on Thursday, September 05, 2019:
Thanks for reporting this as this is a young port and the more feedback
the better. It does indeed seem to be an err - the interrupt stacks
were being correctly aligned to 16 but not the task stack in the 32-bit
version. I have corrected this but the change is not checked in yet.
You may be interested in a few changes that have been made since the
last release in response to feedback - first the way the mtimer compare
register is being updated removes an edge case issue, the mtimer compare
address now works on harts other than the first hart, and the switch
between systems that have a CLINT and those that don’t has been replaced
by requesting the address of the mtimer registers rather than the
address of the CLINT for the case where the mtimer is present without a
CLINT (no longer Si-Five specific). That last change has not been
checked in yet as we are wondering if it can be done in a backward
compatible way as currently it would break existing code.
kj-lin wrote on Friday, September 06, 2019:
Thank you very much for your explanation.
I am looking forward to seeing the update.