Runing FreeRTOS with external HyperRam

gauravpatni wrote on Monday, August 06, 2018:

Dear Support team,

In one of the project we are planning to use FreeRTOS with external HyperRAM S70KL1281 ( ) with STM32L4R5ZI ( having Octal-SPI support )

we need to execute all FreeRTOS functionality from FreeRTOS ( mainly heap memory )

But I have some basic doubts regarding context switching while communicating with External HyperRAM as follows:

  1. as per datasheet of hyperRAM , (S70KL1281 section 3.2Command/Address Bit Assignments ) , it takes several clock cycles to start data transfer .
  2. most importantly data bus of HyperRAM is of 8 bit & RTOS functionality is considering 32 bit ( as MCU is 32 bit ) . So data communication might not be ‘atomic’ .

So what will happen if context switching happens during operation ? how to prevent external HyperRAM data corruption ?


richarddamon wrote on Monday, August 06, 2018:

I am not familiar with that particular combination, but here are my general observations:

The datasheet says that the processor make the external memory look like internal memory, so that means that at the processor level, a request from the chip will processed a pull a bit from that memory into a local cache, transparently to the program.

First, this means that you don’t need to worry about switching in the middle of a operation, the processor will handle the details itself.

It does mean that you will get a slightly increased latency, as such a request will stall the processor (just like a request to other external memories, or sometimes even internal flash). Unless you have nano-second level latency requirements this probably isn’t a concern.

Also, you don’t need to worry about the device being ‘8 bits’, the processor will grab enough data to do the operation.

gauravpatni wrote on Monday, August 06, 2018:

Hi Richard Damon ,

Thanks for your reply .

I will share results after getting assembled PCB with HyperRam , .