RISC-V RV32E

Kernel
1

nakane1chome wrote on Friday, September 06, 2019:

Has anyone adapted the RISC-V port for rv32ec base ISA?
I’ve started to do it but not had time to do much verification (that was more to do with the lack of a CLINT on my core, the new mtimer changes look helpful) . If no one else is working on it I’ll see if I can complete it and contribute back.

2

rtel wrote on Friday, September 06, 2019:

It is not something we have looked at yet, and it is definitely of
interest. We have made a few changes to the RISC-V port recently, and
the mtimer change you mention below has also been made but not checked
in yet. After that there is still one change outstanding, which is to
pass software interrupts out to the application - it would be great if
we can stay in sync on these changes and the code you are creating. Do
you think it would be possible to have the ‘E’ profile as a build time
option in the existing port files?

3

nakane1chome wrote on Sunday, September 08, 2019:

Yes, the ‘rv32e’ is similar enough to the other base ISAs that the same port code can be used.

In portASM.S I simply made the load_x and store_x statements for x16 to x31 conditional on #ifndef __riscv_32e.

For the stack frame size I updated the macro portCONTEXT_SIZE, and then defined that according to if __riscv_32e was defined. (14 registers for rv32e vs 30 registers for other base ABIs).

In pxPortInitialiseStack I also needed to make a change to reduce the space for x11-x31 to x11-x15.

It’s probably possible to test this out on an rv32i core by compiling the code using -march=rv32e and -mabi=ilp32e .

4

rtel wrote on Monday, September 09, 2019:

Thanks for the info - and the tip on how to test without an ‘e’ board
myself.

5

kj-lin wrote on Tuesday, September 10, 2019:

By the way, besides making load_x and store_x statements for x16 to x31 conditional and reducing the space for x11-x31 to x11-x15 in pxPortInitialiseStack(), RV32E should have the portBYTE_ALIGNMENT definition to 8 in portmacro.h file.
RV32E is based on RISC-V EABI and should be 8-byte stack aligned insead of RV32/RV64 16-byte aligned.

  #ifdef __riscv_32e
        #define portBYTE_ALIGNMENT 8
  #else
        #define portBYTE_ALIGNMENT 16
   #endif