RISC-V FreeRTOS Port: Status of support for "compressed" ISA extension

Based on this discussion located in a FreeRTOS-Kernel GitHub ticket #100 (Sorry, I’m a new user so the forum will not let me post a direct link), there seems to be some ambiguity regarding whether or not the FreeRTOS port for RISC-V platforms supports the standard RISC-V ISA extension for compressed instructions. The contributor claims that FreeRTOS does not support the extension, but the author of the ticket points out that this is not documented anywhere, and all the demos seem to indicate that the extension is supported. The ticket has since been closed, but I cannot find any indications in the kernel release notes or pull request history claiming that the extension is or is not supported. Can anyone clarify the status of whether or not the FreeRTOS RISC-V port supports the extension?

Does the compressed ISA introduce or remove any registers over the standard I registers? Or change the alignment requirements? If not, it might just work with the existing port.

As per this spec, the compressed instruction set does not add/remove any register. Therefore, the existing port should work. Let us know if you face any issue in using this port.

Maybe some of the assembly code used in the port layer is only available with the standard (uncompressed) instruction set?