I have cleaned out the AT91SAM7X demo to work with AT91SAM7S instead. Most of the code except the USB CDC task is removed and replaced with my own code. It all compiles and run fine in IAR but I am having issues with Crosswork. The code compiles in crosswork and all initiation seam to work fine exccept when it is time to start all the created tasks. As I understand the "vTaskStartScheduler" function ends by calling "vPortISRStartFirstTask" to start the sceduler. When this is done I get a data abort and the program stucks in the "dabort_handler" loop.
Does anyone have an idea where I should start to look for the problem. Can there be an memmory issue, stack perhaps? The Heap should be fine. I still have arround 100 bytes left on the heap assigned in freertosconfig.h file after all tasks are created. I also use heap_1.c for memory management.
Well, I have the "ldr pc, [PC, #-0xF20]" in my startup.s file. As for global pre processor definitions I have the same as in the demo "SAM7_GCC;THUMB_INTERWORK;SUPERVISOR_START" I can not find the "VECTORED_IRQ_INTERRUPTS" defined anywhere. Should this be defined in the same place, under "solution" in the "common" configuration
I searched the whole FreeRTOS catalog and only found the "VECTORED_IRQ_INTERRUPTS" to be used with Philips LPC210X processor. Is this also needed for the AT91SAM7 series?
Step into the vPortISRStartFirstTask code. Check that the processor is in supervisor mode when this code runs. See the line where the PC register is loaded, at that point all the other registers should be loaded with known values that are obvious ( value 1 in register 1 ect ) is this the case?
when the first task starts the interrupts will be enabled. Is it that you are jumping directly to an interrpt handler that is crashing?
I am compiling for thumb, exccept for the ISRs, which are definedas “naked” and compiled in in arm mode. I can’t check exactly where the crash occuers at the moment, will do later.
Let’s assume it crasshes where you explained, at the actual jump. What is your sugestion in that case?
Only to check that all the registers are correct immediately prior to the jump, that it is in system mode with interrupt disabled, and if all this is so, then see where the heck it goes! It might be worth setting a break point on the IRQ vector as you load the program counter. That way you can see if an interrupt is eventing as soon as the interrupt is enabled as task starts.
I could not get the stock applications to run on a SAM7S with interwork enabled, once I changed all files to compile to full-fat ARM and removed the pre-processor THUMB_INTERWORK define then I was able to get the scheduler running.
I still cannot get thumb applications to work when Crossworks & FreeRTOS on a SAM7S.
Finaly I have managed to get it to work, when canceling out all my own code except for some simple HW initiation The code is basically the AT91SAM7X demo with only the USB task runing. This works fine on the SAM7S now with THUMB_INTERWORK defined. I run all code in THUMB mode eccept for the ISR routines which are in ARM mode,as required.
At this point I beleive that there may be a memmory issue or that I do something unclever when creating my tasks. I’ll look into that tomorrow.
I have one thing thay may be of relevance. I know that all IRS functions must be declared as "naked" and running in ARM mode. When defining a function that are called from within an ISR, does this function need to be running in ARM mode as well? is it required to be "naked"?
No - functions called from the isr can be normal functions.
Declaring the isr naked is just one method, and the way the sam7x demo works. If you look at the str9 demo you will see that only a single isr entry point is defined that saves the context, then all isr functions are just standard functions. Both ways have pros and cons, I don’t want to confuse things, just an alternative.
The code is basically the AT91SAM7X demo with only the USB task runing. This works fine on the SAM7S now with THUMB_INTERWORK defined. I run all code in THUMB mode eccept for the ISR routines which are in ARM mode,as required.