posting event from interrupts configured as wakeup source

I am using FreeRTOS v10.3.0 for iMX RT1052.

I have configured GPT2 timer for 10ms time. GPT2_IRQ is set as wakeup source from system idle.

The sequence of the code is,

start GPT2 timer → enter critical section → enter system idle mode → stay in system idle mode until GPT2_IRQ wakesup from idle mode–> GPT2_IRQ occurs → post event from ISR to task using RTOS API → exit critical section.

The code works except the posting of event from ISR. It does not work as the prio of the IRQ needs to be 3 or more(more than configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY).
If NVIC_SetPriority for GPT2_IRQ is set to 3 or more, the GPT2_IRQ gets masked because while entering critical section the BASE_PRI value gets set to 0x2.

So, I can either set the prio of the GPT2_IRQ to
A)numerical value > configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY (ex:3 or more)
B)numerical value < configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY (ex:0,1)

If I follow A) the interrupt gets masked due to BASE_PRI
and If I follow B) I cannot use RTOS API in the ISR.

Is it possible to achieve what I am doing? Please let me know If I am missing anything.

Did you consider using tickless idle?

The Cortex-M gets around this problem by allowing interrupts to bring a processor out of sleep mode even when interrupts are globally disabled (rather than masked by BASEPRI) - which is how the tickless idle works. That way the processor will come out of sleep mode even though interrupts are disabled, but the interrupt won’t actually execute until interrupts are re-enabled.