Porting FreeRTOS SMP to RISC-V without IPIs:

Kernel
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3

Hi yuecharlie,

FreeRTOS SMP handles yield requests from other cores (via portYIELD_CORE()) at the following places:

  1. Waiting to enter the critical section in prvCheckForRunStateChange()
  2. Checking xYieldPendings when leaving the critical section
  3. Asynchronous yield request through IPIs when task is not in the critical section

The first two synchronous handling mechanisms may not be affected, but the third is impacted by replacing IPIs with shared-memory xYieldRequests.

I can think about the following drawbacks:

Memory-related Issues

  • As Richard mentioned, using shared-memory as IPIs should consider:
    • Memory coherency problems
    • Race condition concerns

Scheduler-related Issues

  • portYIELD_CORE now takes more time to take effect on other cores, resulting in:
    • Unpredictable context switch timing
    • Increased priority inversion duration
    • Delayed response to scheduling events

Performance Impacts

  • Polling xYieldRequests causes system performance impacts including:
    • CPU overhead
    • Increased power consumption

While this solution might work, you might need to carefully evaluate these trade-offs against your system’s requirements, especially regarding real-time constraints and performance needs.

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