New RISC-V Cpu integration

We are trying to run FreeRTOS on our risc-v cpu and after some iterations an addressing problem appears. Cpu gets into freertos trap handler couple of times and then gets stuck because of address that selects the memory region(sram,rom etc…) is 1 bigger than its supposed to be (it should be 16384 instead of 16385 so slave select does not happen). Is there any recommendations you can give in order to understand the root of the problem ?

Thats our disassembly where the problem happens:
thats our dissassembly:

40004e00 <freertos_risc_v_trap_handler>:
40004e00: f8410113 add sp,sp,-124 // where wrong address is calculated
40004e04: 00112223 sw ra,4(sp) // Where cpu gets stuck
40004e08: 00512423 sw t0,8(sp)
40004e0c: 00612623 sw t1,12(sp)
40004e10: 00712823 sw t2,16(sp)
40004e14: 00812a23 sw s0,20(sp)
40004e18: 00912c23 sw s1,24(sp)
40004e1c: 00a12e23 sw a0,28(sp)
40004e20: 02b12023 sw a1,32(sp)
40004e24: 02c12223 sw a2,36(sp)

Our code is a basic one that returns 2 tasks.

Hi - I understand there is an invalid address. What is not clear is whether this is an error in the chip, in the compiler generated assembly code, or a corruption in the software.

Which chip are you using?
Are you running the program out of read only memory, or RAM?

This line just moves the stack pointer. Can you elaborate on what you mean by “wrong address is calculated”? Do you mean that SP is out of range? If yes, it may be because of stack overflow - can you try increasing the stack size?

Actually we also can not figure out what causes the problem. We are using an FPGA so we are in control of the hardware. We can increase ram,rom etc. but i dont think thats the case because we tried to increment all of it but we couldnt solve it.

In our verilog hardware code all the memory regions are selected with 29:14 bits so slave select signal lets us select the memory region. In our case Stack pointer calculation gives us 16385 instead of 16385 so slave select operation does not happen in the hardware.
WhatsApp Image 2024-04-26 at 20.36.43

Strange thing is we tried this with other CPU and it is working but not in our own cpu. We also tried increasing the stack size but it did not work :frowning:

How is this address calculated? Is software involved in this or is it some Verilog issue? Are you able to run bare metal software on the core which does not include FreeRTOS?