I found that there are several NetworkInterface.c of STM32F7(one included in FreeRTOSV10.0.1, one included in amazon-freertos-1.2.7, one found in this forum posted by Hein Tibosch).
Which one is the newest.
Thank you!
Also, if I set ipconfigZERO_COPY_RX_DRIVER=0 and ipconfigZERO_COPY_TX_DRIVER=0. I can not ping my board.
The latest non official release of the STM32F driver can be found here
Eventually that will be merged with the official release, once everyone is satisfied with it.
Hi Hein:
Thank you.
I have one more question. The offical STM32Cube_FW_F7(which contains stm32f7xx_hal_eth.c) is V1.12.0. Should I replace the stm32fxx_hal_eth.c in the STM32Fxxx_driver.7z with stm32f7xx_hal_eth.c in the STM32Cube_FW_F7_V1.12.0?
I think there are some essential differences. Please use the unified stm32fxx_hal_eth.c from the 7-zip and the corresponding header files. That should work for both F4 and F7. Please define the correct part as:
#define STM32F7xx 1
Make sure that the header file stm32f7xx_hal_eth.h from STM32Cube does not appear in the include path (-I).
The Phy is LAN8720A and its status is 100MBPS fullduplex.
PHY ID 7C0F0
xPhyReset: phyBMCR_RESET 0 ready
$:+TCP: advertise: 01E1 config 1000
prvEthernetUpdateConfig: LS mask 00 Force 1
Autonego ready: 00000004: full duplex 100 mbit high status
The IPv4 stack and iperf configurations are:
ipconfigZERO_COPY_RX_DRIVER ( 1 )
ipconfigZERO_COPY_TX_DRIVER ( 1 )
ipconfigIPERF_TX_BUFSIZE ( 16 * 1024 ) /* Units of bytes. /
ipconfigIPERF_TX_WINSIZE ( 4 ) / Size in units of MSS /
ipconfigIPERF_RX_BUFSIZE ( ( 16 * 1024 ) - 1 ) / Units of bytes. /
ipconfigIPERF_RX_WINSIZE ( 8 ) / Size in units of MSS */
.\iperf3.exe -c 192.170.1.99 --port 5001 --time 6
Connecting to host 192.170.1.99, port 5001
[ 4] local 192.170.1.198 port 3197 connected to 192.170.1.99 port 5001
[ ID] Interval Transfer Bandwidth
[ 4] 0.00-1.00 sec 256 KBytes 2.10 Mbits/sec
[ 4] 1.00-2.00 sec 0.00 Bytes 0.00 bits/sec
[ 4] 2.00-3.00 sec 0.00 Bytes 0.00 bits/sec
[ 4] 3.00-4.00 sec 0.00 Bytes 0.00 bits/sec
Can you start is as the examples in iperf_task_v…c :
iperf3 -c 192.170.1.99 --port 5001 --bytes 100M // from host to device
iperf3 -c 192.170.1.99 --port 5001 --bytes 100M -R // from device to host
Or less than a 100 MB if you want.
The Phy is LAN8720A and its status is 100MBPS fullduplex.
PHY ID 7C0F0
xPhyReset: phyBMCR_RESET 0 ready
$:+TCP: advertise: 01E1 config 1000
prvEthernetUpdateConfig: LS mask 00 Force 1
Autonego ready: 00000004: full duplex 100 mbit high status
That all looks OK, also your IPERF settings.
NetworkInterface.c of STM32F7
From the older NetworkInterface/STM32F7 directory? Or from the 7-zip mentioned here above?
Just to be sure, I’ll attach my latest version of the iperf server: iperf_task_v3_0d.c
Hi Hein:
Thank you for your help.
The IPv4 stack and eth dirver do not work normal with D-CACHE enabled.
When I disable the D-CACHE.It seems working fine now.
Here is the iperf test result with iperf_task_v3_0d.c:
λ .\iperf3.exe -c 192.170.1.99 --port 5001 --bytes 100M
Connecting to host 192.170.1.99, port 5001
[ 4] local 192.170.1.198 port 12461 connected to 192.170.1.99 port 5001
[ ID] Interval Transfer Bandwidth
[ 4] 0.00-1.00 sec 11.0 MBytes 92.3 Mbits/sec
[ 4] 1.00-2.00 sec 11.0 MBytes 92.3 Mbits/sec
[ 4] 2.00-3.00 sec 11.1 MBytes 93.3 Mbits/sec
[ 4] 3.00-4.00 sec 11.0 MBytes 92.3 Mbits/sec
[ 4] 4.00-5.00 sec 11.0 MBytes 92.3 Mbits/sec
[ 4] 5.00-6.00 sec 11.1 MBytes 93.3 Mbits/sec
[ 4] 6.00-7.00 sec 11.0 MBytes 92.3 Mbits/sec
[ 4] 7.00-8.00 sec 11.1 MBytes 93.3 Mbits/sec
[ 4] 8.00-9.00 sec 11.0 MBytes 92.3 Mbits/sec
[ 4] 9.00-9.05 sec 640 KBytes 107 Mbits/sec
Those are perfect results, 92 and 82 % usage of the bandwidth!
When D-Cache was enabled, did you also define NETWORK_BUFFERS_CACHED = 1?
And did you see these comments:
/* Put the DMA descriptors in '.first_data'.
This is important for STM32F7, which has an L1 data cache.
The first 64KB of the SRAM is not cached. */
/* Ethernet Rx MA Descriptor */
__attribute__ ((aligned (32)))
__attribute__ ((section(".first_data")))
ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];
When using D-Cache, the table DMARxDscrTab is expected to be placed in a non-cacheable memory range.
But for a STM32F7 it might not work. I just haven’t had the time to work on it.
I would recommend continuing with your current settings. Later on, I will work out the D-Cache option and come back to it.
Thanks a lot for reporting every thing. By doing so, you have also helped other users
Are there any plans in the near future to look at the STM32H7 part? It appears that the ethernet MAC peripheral is almost entirely unchanged from the F7, with the only difference that should matter being the DMA peripheral differences from H7 to F7. I have to admit that it is a little beyond me to do the conversion of NetworkInterface.c from F7 to H7 myself, but I hugely appreciate all the awesome work that has been done on the F7 and F4 ports for ethernet, which is working great for me!