The bit is used to tell you which stack was in use when the exception occurs - you will have to read the exception handling section of the Cortex-M user manual for the details.
The Link Register (LR) is register R14. It stores the return information
for subroutines, function calls, and exceptions. On reset, the processor
sets the LR value to 0xFFFFFFFF.
Nothing told about bit2 of the Link Register. Can you point me a piece of
information that explains it?
On Mon, Dec 8, 2014 at 9:55 PM, Real Time Engineers ltd. rtel@users.sf.net
wrote:
The bit is used to tell you which stack was in use when the exception
occurs - you will have to read the exception handling section of the
Cortex-M user manual for the details.
The Link Register (LR) is register R14. It stores the return information
for subroutines, function calls, and exceptions. On reset, the processor
sets the LR value to 0xFFFFFFFF.
Nothing told about bit2 of the Link Register. Can you point me a piece of
information that explains it?
On Mon, Dec 8, 2014 at 9:55 PM, Real Time Engineers ltd. rtel@users.sf.net
wrote:
The bit is used to tell you which stack was in use when the exception
occurs - you will have to read the exception handling section of the
Cortex-M user manual for the details.
Regards.