MSP/PSP on Cortex-M3

znatok wrote on Monday, December 08, 2014:

Hi,
I’m writing my own core dump functionality and would like to get an
explanations about below code:

/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
static void HardFault_Handler(void)
{
__asm volatile
(
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
" ldr r1, [r0, #24] \n"
" ldr r2, handler2_address_const \n"
" bx r2 \n"
" handler2_address_const: .word prvGetRegistersFromStack \n"
);
}

  1. How the lr (link register) bit 2 is related to MSP/PSP usage?
  2. What is the FreeRTOS policy in selecting MSP or PSP?
  3. I assume this instruction

ldr r1, [r0, #24]

is used to load PC in r1 and pass it as second argument to
prvGetRegistersFromStack, what for?

Thanks.

rtel wrote on Monday, December 08, 2014:

The bit is used to tell you which stack was in use when the exception occurs - you will have to read the exception handling section of the Cortex-M user manual for the details.

Regards.

znatok wrote on Monday, December 08, 2014:

This is all I can find about Link Register in Cortex-M3 (at
http://infocenter.arm.com/) :

Link Register

The Link Register (LR) is register R14. It stores the return information
for subroutines, function calls, and exceptions. On reset, the processor
sets the LR value to 0xFFFFFFFF.

Nothing told about bit2 of the Link Register. Can you point me a piece of
information that explains it?

On Mon, Dec 8, 2014 at 9:55 PM, Real Time Engineers ltd. rtel@users.sf.net
wrote:

The bit is used to tell you which stack was in use when the exception
occurs - you will have to read the exception handling section of the
Cortex-M user manual for the details.

Regards.

MSP/PSP on Cortex-M3
https://sourceforge.net/p/freertos/discussion/382005/thread/1fb1b35d/?limit=25#ef07

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znatok wrote on Monday, December 08, 2014:

OK,
Found it:

Table 2.17. Exception return behavior
EXC_RETURNDescription0xFFFFFFF1

Return to Handler mode.

Exception return gets state from the main stack.

Execution uses MSP after return.
0xFFFFFFF9

Return to Thread mode.

Exception Return get state from the main stack.

Execution uses MSP after return.
0xFFFFFFFD

Return to Thread mode.

Exception return gets state from the process stack.

Execution uses PSP after return.
All other valuesReserved.

On Mon, Dec 8, 2014 at 10:55 PM, Ella znatok@users.sf.net wrote:

This is all I can find about Link Register in Cortex-M3 (at
http://infocenter.arm.com/) :

Link Register

The Link Register (LR) is register R14. It stores the return information
for subroutines, function calls, and exceptions. On reset, the processor
sets the LR value to 0xFFFFFFFF.

Nothing told about bit2 of the Link Register. Can you point me a piece of
information that explains it?

On Mon, Dec 8, 2014 at 9:55 PM, Real Time Engineers ltd. rtel@users.sf.net
wrote:

The bit is used to tell you which stack was in use when the exception
occurs - you will have to read the exception handling section of the
Cortex-M user manual for the details.
Regards.

MSP/PSP on Cortex-M3

https://sourceforge.net/p/freertos/discussion/382005/thread/1fb1b35d/?limit=25#ef07

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https://sourceforge.net/p/freertos/discussion/382005/

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MSP/PSP on Cortex-M3
http://sourceforge.net/p/freertos/discussion/382005/thread/1fb1b35d/?limit=25#ef07/03bd

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rtel wrote on Monday, December 08, 2014:

I just googled “cortex-M exception entry LR” and the first hit was
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/Babefdjc.html
which tells me about the LR in an exception handler “The lowest five
bits of this value provide information on the return stack and processor
mode”.

Regards.