Missing initialization of the Cortex-M0 SysTick register on FreeRTOS v.7.8.0

linyola wrote on Thursday, February 27, 2014:

I’m using FreeRTOS since 7.4.0 and since then I have to add to every update the initialization of the systick register on “port.c” file from the “/Source/portable/GCC/ARM_CM0/” folder.
The problem is that the code initialize the portNVIC_SYSTICK_LOAD with the calculated clock value, but after that line not initializes the portNVIC_SYSTICK_VAL to 0. It causes a start-up random delay of the first tick, because the we have to wait the transition from 1->0 from a counter that have a random number.
Remember that the value of this register after a reset is: Unknown.
On a speedy hardware’s this is not important but in battery designs with low frequency clocks this matter.

The patch is very simple, on "/Source/portable/GCC/ARM_CM0/port.c" add:

Add the definition of the register:

#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t *) 0xe000e010 )
#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t *) 0xe000e014 )
#define portNVIC_SYSTICK_VAL ( ( volatile uint32_t *) 0xe000e018 ) // <-- new line
#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )
#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )

Add the initialization of the register to zero:

/* Configure SysTick to interrupt at the requested rate. */
*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
*(portNVIC_SYSTICK_VAL) = 0; // <-- new line

rtel wrote on Thursday, February 27, 2014:

Thanks for the info, we will investigate this asap.