I am a college student and recently working on designing a simple riscv cpu. If I want my own desigined cpu able to be ported to freertos, what criteria does the cpu need to satisfy?
Such as how many levels of interrupts that the cpu need to support?
I looked up many docs but did’t find anything useful
As far as interrupts, you only need one priority level, FreeRTOS does not need nesting interrupts, and systems which do not nest interrupts are actually simpler to provide a porting layer for (but likely less performant).
I would look at the documentation for making a port, and look at a couple of typical ports. Probably the biggest are the ability to save ALL of the state of a task, change the stack to new regions, and get periodic interrupts for timing.
To add to Richard’s response, here is the FreeRTOS RISCV port: FreeRTOS-Kernel/portable/GCC/RISC-V at main · FreeRTOS/FreeRTOS-Kernel · GitHub
Here is the documentation about using FreeRTOS in RISCV: FreeRTOS for RISC-V RV32 and RV64
Thanks.
Sorry for my late reply.
Very grateful for your advice as it is hard to getting into a new field.
@richard-damon @aggarg
To add a little tidbit (though it’s not exactly CPU related): The footprint required by FreeRTOS is very very minimal. FreeRTOS will run on a Cortex M0 w/ as little as 256k Flash (possibly also 128) and 8k of RAM, leaving the major part of memory to applications (which will still by definition be quite restricted which however is not the fault of the RTOS ). Naturally you’ll need to compromise on functionality (eg there will very likely not be dynamic memory allocation, heap_1 must suffice).
I’ve run FreeRTOS in MUCH smaller chips than that. 32k flash can be enough. 8k ram is probably about as small as you can get since you need at least two task stacks (one for idle) as a minimum useful system so 4k is likely too small.