Method how to deffer interrupt priority below configMAXSYSCALLINTERRUPTPRIORITY

mrazoun wrote on Thursday, May 24, 2018:

Hi,
I need to catch UART’s interrupt with low latency. It means I need to set UART’s interrupt priority higher than configMAXSYSCALLINTERRUPTPRIORITY . I also need to recognize end of incoming data and after that to send notification to task.
Please, can you recomend me any mechanism, which will allow it ?

My idea :

  • receive data with high priority, with short as possible routine, save data into circular buffer
  • inform some way second part of routine, that new data was come
  • in second part of routine recognize if end of message was come
  • second part of routine should have lower priority than configMAXSYSCALLINTERRUPTPRIORITY
  • if end of data was recognized to send a notification to task

The QUESTION is how to inform second part of routine. SWI instruction is not present in used uP.

My conditions:
EFM32GG Sylabs, Cortex-M3 core

Thank’s in advance for your recomendation.
BR,
Zdenek

gezab wrote on Thursday, May 24, 2018:

how about using dma and/or fifo?

On Thu, 24 May 2018 13:51 Zdenek Brancusky, mrazoun@users.sourceforge.net
wrote:

Hi,
I need to catch UART’s interrupt with low latency. It means I need to set
UART’s interrupt priority higher than configMAXSYSCALLINTERRUPTPRIORITY . I
also need to recognize end of incoming data and after that to send
notification to task.
Please, can you recomend me any mechanism, which will allow it ?

My idea :

  • receive data with high priority, with short as possible routine, save
    data into circular buffer
  • inform some way second part of routine, that new data was come
  • in second part of routine recognize if end of message was come
  • second part of routine should have lower priority than
    configMAXSYSCALLINTERRUPTPRIORITY
  • if end of data was recognized to send a notification to task

The QUESTION is how to inform second part of routine. SWI instruction is
not present in used uP.

My conditions:
EFM32GG Sylabs, Cortex-M3 core

Thank’s in advance for you recomendation.
BR,
Zdenek

Method how to deffer interrupt priority below
configMAXSYSCALLINTERRUPTPRIORITY
https://sourceforge.net/p/freertos/discussion/382005/thread/dea22ee7/?limit=25#6c8c

Sent from sourceforge.net because you indicated interest in
https://sourceforge.net/p/freertos/discussion/382005/

To unsubscribe from further messages, please visit
https://sourceforge.net/auth/subscriptions/

richard_damon wrote on Thursday, May 24, 2018:

First, needing low latency doesn’t necessarily imply needing to be above MAXSYSCALLINTERRUPTPRIORITY, as the critical section which disable to that level should all be very short, so unless you really need latency of an order of a few instructions, you can probably live below that. If you have a UART with that sort of need, you either are sending data at an extreame data rate, where using DMA is likely the better option as mentioned above, or the UART is badlyy designed (NO receive buffer so you need to service in 1 bit time).

That said, the way to have a routine above the Priority line communicate with FreeRTOS is it needs to trigger antoher interrupt that is below the line. On some machine that could be a SWI, or it could just be an interrupt for an unused peripheral that you can manually set the interrrupt request flag (common on Arm Cores).

mrazoun wrote on Thursday, May 24, 2018:

LEUART1 doesn’t have FIFO feature.
DMA usage is problematic because there is not know’n how many of bytes data packet will have (RX packet), I know there is possible to poll it with defined timeout. Maybe better solution will exist.
Thank’s for your answer.
Zdenek

richard_damon wrote on Thursday, May 24, 2018:

Not having a FIFO says you have 1 character time to repond to the interrupt. At 115200 baud you get about 80 microseconds, which is forever for a modern microprocessor.

One way to use DMA here is put a timeout, so if you don’t get a DMA completion interrupt after a bit (and thus likely data transmission has terminated), you check and drain. First byte of message reception based on interrupts and turns on the DMA and timer.