Memory Constrained FreeRTOS in Xilinx FPGA

Hello All,

I am new to FreeRTOS. I am working on an application that runs on an Arm Processor that belongs to a Xilinx FPGA. The design does not have DDR. It has the processor’s on-chip memory, as well as some block memory, available to it. Out of the box, the Xilinx FreeRTOS HelloWorld example application appears to big to fit entirely in OCM. I am looking for guidance and/or resources on how I might successfully build FreeRTOS to take advantages of the resources I have available to me through modification of its configuration files and/or linker files. That is processor OCM and external BRAM. Thank you in advance for any guidance you may have.

What resources do you have?

Are you familiar with reading map files to see what is consuming most of your resources so you can optimise? That is more to do with your compiler and linker than FreeRTOS. You can also ensure the linked is removing unused code.

Thanks for the reply. The processor has 256K of OCM memory and I have access to another 128K or so that in the FPGA fabric. Looking at the map files is one of those things I can remind myself how to do when their is a need. I spend most of my time on the logic design side. Additionally, I will look at the specific options for removing unused code in the design elf file.

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I’m curious, which Zynq is it ? An Ultrascale+ MPSoC using one of the RPUs ?

256k is a LOT of memory for FreeRTOS, I have built systems with 32k ROM and 16k RAM without needing “extraordinary” measures to fit (just managing project expectations). It is easy to use parts of the standard library that just balloon the code, and printf, which is common for “hello world” is one of them.