I am looking at using the MIPS M14K port for a product. I notice that the only FreeRTOS port for the M14K does not make use (take advantage of) the shadow registers. On interrupt entry it saves task context straight away before servicing the interrupt. I can see why this is done - it puts everything in a consistent state, ready for any context switch that the ISR may cause. I suppose that if you take the view that any ISR that is doing ‘real work’ is likely to post a semaphore or send a message, and that a context switch out of ISR is the typical case, then this makes sense. (I did the same in an RTOS I once wrote). However, there may be cases where we have interrupts that we need to service very quickly, even without the need to communicate with a task, and the speed advantage of the shadow registers is highly desirable. Has anyone looked at the possibility of tweaking the port to do this? Or am I on my own on this?
A related side question, which is more architectural: I notice that FreeRTOS does not have a proper scheduler lock (disable pre-emption mode). Rather it relies heavily on disabling/enabling interrupts for critical sections. Has anyone attempted to address this in any of the ports? It should be simple enough to add a soft lock to the scheduler, so you prevent (actually defer) thread switches during critical sections, without affecting interrupt latency? Quite happy to hack this in myself, but if someone has already done it…