Interrupts being disabled

seanbzd wrote on Friday, August 07, 2015:

I’m working on the FreeRTOS port on the zynq platform. I am doing some SPI transfers in the ISR handler and once every few minutes, i’m getting errors during the SPI transfers (RX Buffer overrun and Tx Buffer underrun). I believe these errors are a result of interrupts being disabled.
We have several tasks, but if I disable a particular task(happens to be the highest priority task on our system), I do not see the SPI transfer errors. So, I’m thinking that something this task is doing is causing the interrupts being disabled that is affecting the SPI transfers.
Question is what APIs should I be looking for that could potentially be disabling interrupts. I searched for taskENTER_CRITICAL_SECTION but we are not using it. Can you point me to other calls that could be disabling interrupts. I see that the xSemaphoreTake() and xSemaphoreGive() would also disable interrupts but I suppose it is done so very briefly that it should not affect the SPI transfers.

Thanks for your help.

heinbali01 wrote on Friday, August 07, 2015:

Hi Sean,

I’m afraid that you don’t provide enough information to give a satisfying answer.

At what speed do you run SPI?
Is it a byte-by-byte transfer or do you use DMA?
Is your Zynq the SPI Master?
( making a CPU a SPI slave is always very problematic )

Who is delivering the data for the SPI, is that a regular task? Does that task get enough attention from the CPU when your high-priority task is running?
Do the TX buffers get filled on time?
Do the RX buffers get flushed on time?
Are RX buffers available when a burst of data comes in?

When interrupts are disabled in the FreeRTOS kernel, it happens indeed very briefly.

The Zynq is a very fast CPU, I suppose you have it running at 666 Mhz? Or less?

Are you sending a lot of SPI data? If you are sending KB’s of data, I would definitely consider using DMA channels.


lciummo wrote on Friday, August 07, 2015:

Sean. I had similar problem with SPI. See code below for example of disabling ints…

// Clear tranfer count register
// SPI0_TCR = 0;
int spi_cnt;


for (spi_cnt = 0; spi_cnt < BYTES_TO_READ; spi_cnt++) {
			| SPI_PUSHR_CTAS(0));
	//while (!(SPI0_SR & SPI_SR_TFFF_MASK)  );

	command = spi_cnt + 1;
	while (!(SPI0_SR & SPI_SR_RFDF_MASK))
	unsigned char byte;
	encoder[spi_cnt] = SPI0_POPR;
	SPI0_SR = SPI_SR_RFDF_MASK; // clear the reception flag (not self-clearing)

	//printf("byte read %0x\n",SPI0_POPR );
// Last byte transfer/receiver
command = 0xff;
while (!(SPI0_SR & SPI_SR_TFFF_MASK))
	;  // wait for transmit

while (!(SPI0_SR & SPI_SR_RFDF_MASK))

unsigned char junk = SPI0_POPR;
SPI0_SR = SPI_SR_RFDF_MASK;  // clear the reception flag (not self-clearing)

unsigned long int encRaw = 0;
for (int k = 5; k > 1; k--) {  //5,4,3,2
	encRaw = (encRaw << 8) + encoder[k];

#ifdef ENDAT22
encRaw = encRaw >> 1;

e-christenson wrote on Saturday, August 08, 2015:

Wait a minute…I don’t particularly know the Zynq CPU… but if it is running at multiple hundred MHz speeds, I expect it has multiple priority levels within the CPU, and, at least on the port I am familiar with, CPU priority levels and RTOS priority levels are different animals, so we need to be extremely careful about that.

On the Microchip dsPIC30F architecture, all of the tasks run at CPU priority zero, the freeRTOS kernel runs at CPU priority 1, and there are additional, higher CPU priorities available for interrupts such as the SPI handler.

I also suggest you AUDIT the source code for the meanings of the critical section and disable interrupts primitives…you will need to know exactly what those do in your architecture. On the pic, both of those simply raise the current CPU priority level to that of the RTOS priority.

Hope this helps!