Interrupt priority of idle task.

yyang2000 wrote on Friday, September 05, 2008:

Hi, I am really confusing the tskIDLE_PRIORITY is defined to 0 in the demo of Cortex_LM3X_IAR_KEIL, which means the idle task has the highest priority. But the Cortex-M3 interrupt priority has been specifically mentioned in the Demo App Introduction as below.
A special note for Cortex M3 users: Remember that Cortex M3 cores use numerically low priority numbers to represent HIGH priority interrupts, which can seem counter-intuitive and is easy to forget! If you wish to assign an interrupt a low priority do NOT assign it a priority of 0 (or other low numeric value) as this can result in the interrupt actually having the highest priority in the system - and therefore potentially make your system crash if this priority is above configMAX_SYSCALL_INTERRUPT_PRIORITY.
The idle task should be the lowest priority task that it can be preempted by other tasks who has higher interrupt priority.  I wonder if anyone can answer my question. Why the tskIDLE_PRIORITY is set to 0?
Bill Yang

richard_damon wrote on Friday, September 05, 2008:

You are confusing TASK priorities with INTERRUPT priorities. INTERRUPT priorities are set by the hardware, and the Cortex M3 defines high numbers as low priority and low numbers as high priority. TASK priorities are controlled by the software (in this case FreeRTOS), and in this case define 0 as lowest and higher numbers have higher priority. Switching between tasks is totally controlled by software (and maybe triggered by an interrupt), and unless they define 1<0, an Idle task priority of 0 will yield to any higher priority task on a call to the task scheduler.

davedoors wrote on Friday, September 05, 2008:

You are confusing the task priority with the interrupt priority.

All FreeRTOS tasks, for all architectures, use 0 to be the lowest TASK priority and configMAX_PRIORITIES - 1 to be the highest TASK priority. At priority 0 the idle task is therefore assigned the lowest priority you can assign a task.

Most architectures also use 0 or 1 to be the lowest INTERRUPT priority so the tick interrupt will also be assigned a priority 0 or 1. The cortex does the opposite which is why the text you quote is given. On the Cortex 255 is the lowest priority and 0 is the highest priority. The Cortex ports assign the tick interrupt a priority of 255 so it is the lowest priority interrupt.

The task priority and interrupt priority are two very different things.

yyang2000 wrote on Friday, September 05, 2008:

Thank you, I got it.
Bill Yang