Interrupt latency and context switch time

nobody wrote on Wednesday, April 27, 2005:

Does anyone know how long interrupts are disabled and how long FreeRTOS needs to switch to the next task on an AMR7 (Philips LPC21xx) @ 60MHz?

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I also want to know the answer.

That is a very specific question - generally we would use the number of instruction cycles rather than an absolute time. The ARM7 is somewhat older than chips I’ve used recently (you are reply to a 17 year old post :grinning: ) but there is some information for Cortex-M here:

thx, XDDDD
Yes, I originally wanted to re post, but after searching, I found that someone wanted to know this performance data 17 years ago. So I just hitchhiked.

What is the context switch time?

Context switch times are dependent on the port, compiler and configuration. A context switch time of 84 CPU cycles was obtained under the following test conditions:

If the dominant frequency is 100MHz.
1us/100*84=0.84us。(So small, it seems negligible.)
Is it right for me to calculate the FREERTOS system overhead time like this?