How to use ddr by PicoZed 7015/7030 correctly


I am new to Zynq 7000 programming. I use lwip UDP server template from Vitis on PicoZed 7015/7030 (FreeRTOS). The purpose is to collect data using DDR3 (~160 MB) at specific address, and send it via UDP protocol. Sending works well. But when I access to the device ddr memory to get saved data, it is partially crushed (it means the data is partially updated). If I use only 60 KB of ddr storage space ( it allows to get short system time between ddr data writing, and sending after that), the system works correct.

So, the question: is there any ways to control or lock ddr-memory for personal usage on Zynq 7000. It will be greate, if someone points my any tutorials or sources to study.


Hi - thanks for your post. Is it related to FreeRTOS? By which I mean, are you able to access the memory in the way you want when FreeRTOS isn’t used (so, bare metal, or before calling vTaskStartScheduler()) but not when FreeRTOS is running? If it isn’t FreeRTOS related then I recommend asking on a Xilinx forum as we prefer to keep questions here strictly related to FreeRTOS to ensure it remains a valuable FreeRTOS resource as apposed to another general embedded system resource. Thanks.

Thank you for your answer. I think that it is related to FreeRTOS, cause I have found lately that FreeRTOS uses caching. Now I think there is wrong usage of caching mechanism at my FreeRTOS code. It is, cause now stored data is being receiving by UDP (only the caching code was added to the project, all the other parts were not changed). Each datagram must include (by code) a whole sequential memory data set. But the received datagram has random data displacement. It means the datagram is whole and is not sequential. Am I right, it is caching troubles?

Please reply me, if you’re still thinking I should close the post, or change the topic.

It will be greate, if someone points me some sources or examples of correct FreeRTOS usage of the caching mechanism. Thanks.

Which caching are you talking about?

This part is not clear. Are you saying that you do not receive data that you send? In other words, the data you send over UDP is getting corrupted?

Also, did you try the same scenario without FreeRTOS and does it work correctly?

I’m talking about CPU cache.

I found out after your questions that sended and received UDP-datagrams matched. It meant, the network part was operating well.

I could not use the same scenario without FreeRTOS at that time, cause there were not any ways to show saved data.

Thanks for your questions! It helps us to move to the solution of the problem!

Thanks for the help!

We were able to solve the problem. There were several troubles in the FreeRTOS project at the same time. As a result, it became difficult to separate them and fix.

To solve the trouble described in this post we disable CPU caching of ddr memory block using Xil_SetTlbAttributes() function (there are other ways to solve). It is described in the document referred to as the “Xilinx Standalone Library Documentation: BSP and Libraries Document Collection (UG643)”.

If you need to use CPU caching in your project, then refer to the same documentation (UG643) and find out “Arm Cortex-A9 Processor Cache Functions” chapter. There is information about correct usage of CPU caching at the chapter. I think it is useful for FreeRTOS projects development.

Thank you for taking time to report back!