rtel wrote on Wednesday, April 15, 2009:
Some of the Cortex M3 and also I think PIC32 demos include a 20KHz interrupt that is assigned a priority above any interrupt priority used by the kernel. The priority is also above the priority that gets masked within critical sections. The idea is to demonstrate that interrupt service routines can be defined to perform functions that require very accurate timing. The priority assignment being above that masked by critical sections and above the kernel interrupt priority means the 20KHz interrupt should never get delayed or otherwise effected by something the kernel is doing. To prove this the 20KHz ISR just measures the time between its invocations to calculate the jitter - it uses a timer peripheral that is running at a fast rate to take a measurement in nano seconds.
I have probably managed to make that sound much more complex than it actually is, but the important thing to note is that the jitter being measured is the jitter in the 20KHz interrupt NOT the jitter in the RTOS tick interrupt. No adjustment in the RTOS tick is needed unless the application is doing something that means the tick interrupt cannot execute for a period greater than one tick.
Again I think I made that second bit sound more complex than it actually is - its been a long day!