How does the CCS Cortex-R4 Example run?

Kernel
1

I don’t have a TI Launchpad at hand to test, but I had look at the code, and wonder how this port does even compile, or if it does, how it should successfully run.

File portable/CCS/ARM_Cortex-R4/portmacro.h declares a SWI_ALIAS:

/* Scheduler utilities. */
#pragma SWI_ALIAS( vPortYield, 0 )
extern void vPortYield( void );
#define portYIELD()                 vPortYield()

but in File portable/CCS/ARM_Cortex-R4/portASM.asm there is no table that implements the SWI alias.

So I wonder how this can work? Where does portYIELD jump to?

The code I checked is the current main (7215c89aa81501f60af8df68dfa99fc2c118a293).

2

This is a compiler feature - https://downloads.ti.com/docs/esd/SPNU151/the-swi-alias-pragma-spnu1513554.html.

Let us know if you face any problem in using this port.

3

Ah okay thanks for the clarification, I didn’t known that SWI_ALIAS automatically remap to interrupts, I only knew about the table feature in assembler files.