Has anybody ported FreeRtos on S3C4510B?

Kernel
1

aeyes wrote on Thursday, August 07, 2008:

Hi ,

    I am trying to port FreeRoos on Samsung S3C4510 b , skyeye simulator . I am using the existing LPC2106 port as it also has a standard ARM7TDMI core . I made the necessary changes to the timer in the prvsetuptimer function specific to Samsung .

  The application starts , I know this because I have put checkpoints at various sectonsof the RTOS code, but then it hangs somewhere . I am unable to trace where it hangs .

  Please note I have not used a hardware yet for this port. Has anyone ported FreeRtos on this processor ?

Please advise .

Regards

 

2

rtel wrote on Thursday, August 07, 2008:

Also check your startup code.  You need a stack for Supervisor and IRQ modes as a minimum, and you need to call main() from Supervisor mode.

I don’t know how accurate the SkyEye simulator is but I know there are other people using it.

Regards.

3

aeyes wrote on Thursday, August 07, 2008:

Hi Richard ,

Thanks a lot .

I will paste the stsrtup file for your reference . The first problem is that the interrupts are not gettign disabled somehow when the code enters the main . It could be a simulator problem , I have posted a mail at the skyeye forum too regarding this .

Also I have edited only the prvsetuptimer function of the code to accomodate the S3C4510b timer . I have given an arbitrary delay for the timer which is a long one . The timer setup is fine as I have checked running the timer on the simulator . Also I put a endless for loop at the end of the code on prvtimer setup to check if the timer is running , and the timer runs.

Also S3C4510b hass a non vectored interrupt structure so I have dedicated the IRQ interrupt request for the timer interrupt, so at the IRQ ISR I have given a branch to the tick ISR routine directly . I have removed the naked attribute and handling the return from interrupt at the assembly level itself .

I am using the Yagarto GNU compiler. I am setting upma stack for the Supervisor and IRQ modes in the startup . I have borrowed the stsrtup routing from somewhere and made the necessary changes.

I am creatijgn2 tasks and trying to run them , the code starts running as I have put various check points in the RTOS source which sends characters out through the UART to indicate a particular section of the code has been reaches, but I am unable to trace it to where it finally hangs.

Also since I am new to embedded development on the whole , I have issues in running GDB and getting a stack dump , but I am working on it .

Pasting the startup code below for you to have a look . Please note that just before the branch to the main routine I have moved to the supervisor mode and disabled the interrupts , but still the interrupts did not get disabled.

Thank you .

/*************************************************************************/
/*  crt.S */
/* S3C4510 */
/*************************************************************************/
@ .include "S3C4510.mac"

.EQU LOCKOUT, 0xC0
.EQU MODE_MASK, 0x1F
.EQU UDF_MODE, 0x1B
.EQU ABT_MODE, 0x17
.EQU SUP_MODE, 0x13
@ SVC
.EQU IRQ_MODE, 0x12
@  IRQ
.EQU FIQ_MODE, 0x11
@  FIQ
.EQU USR_MODE, 0x10
@ USR
.equ I_BIT, 0x80
/* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40
/* when F bit is set, FIQ is disabled */
.set
MODE_SVC, 0x13 /* Supervisor Mode */

ENTRY:
B Reset_Handler
B SystemUndefinedHandler
B SystemSwiHandler
B SystemPrefetchHandler
B SystemAbortHandler
B SystemReserv
B SystemIrqHandler
B SystemFiqHandler

.global Reset_Handler
Reset_Handler:

LDR r0, =0x3FF0000

LDR r1, =0xe7ffff90

STR r1, [r0]

LDR r0, =0x3ff3008
LDR r1, =0x6000000
@ Trying to configure EXTACON0 with tACC1 = 5 cycles
STR r1, [r0]

.ifdef
ROM
LDR r0, =SystemInitDataSDRAM

LDMIA r0, {r1-r12}

LDR r0, =0x3FF0000 + 0x3010

STMIA r0, {r1-r12}

.endif

.extern Image_RO_Limit
.extern Image_RW_Base

.extern Image_ZI_Base
.extern Image_ZI_Limit
LDR r0, =Image_RO_Limit

LDR r1, =Image_RW_Base

LDR r3, =Image_ZI_Base

CMP r0, r1

BEQ LOOP1
LOOP0:
CMP r1, r3

LDRCC r2, [r0], #4
STRCC r2, [r1], #4
BCC LOOP0
LOOP1:
LDR r1, =Image_ZI_Limit

MOV r2, #0
LOOP2:
CMP r3, r1

STRCC r2, [r3], #4
BCC LOOP2

INITIALIZE_STACK:
MRS r0, cpsr
BIC r0, r0, #LOCKOUT | MODE_MASK
ORR r2, r0, #USR_MODE
ORR r1, r0, #LOCKOUT | FIQ_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =FIQ_STACK

ORR r1, r0, #LOCKOUT | IRQ_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =IRQ_STACK

ORR r1, r0, #LOCKOUT | ABT_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =ABT_STACK

ORR r1, r0, #LOCKOUT | UDF_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =UDF_STACK

ORR r1, r0, #LOCKOUT | SUP_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =SUP_STACK

MRS r0, cpsr
BIC r0, r0, #LOCKOUT | MODE_MASK
ORR r1, r0, #USR_MODE
MSR cpsr_cf, r0
LDR sp, =USR_STACK
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT    # this is where I have tried to disable the IRQ and FIQ ISR but it has no effect :frowning: …

.extern main
BL main

SystemUndefinedHandler:
B SystemUndefinedHandler
SystemSwiHandler:
B SystemSwiHandler
MakeSVC:
B MakeSVC
SystemPrefetchHandler:
B SystemPrefetchHandler
SystemAbortHandler:
B SystemAbortHandler
SystemReserv:
B SystemReserv
SystemIrqHandler:

.extern ISR_IrqHandler
STMFD sp!, {r0-r12, lr}

BL ISR_IrqHandler

LDMFD sp!, {r0-r12, lr}

SUBS pc, lr, #4

SystemFiqHandler:

.extern ISR_FiqHandler
STMFD sp!, {r0-r7, lr}

BL ISR_FiqHandler

LDMFD sp!, {r0-r7, lr}

SUBS pc, lr, #4

SystemInitDataSDRAM:
.long 0x0a7fff0f @;EXTDBWTH
#.long 0x01000060 @;ROMCON0
.long 0x02000060 @;ROMCON0
#.long 0x13044060 @;ROMCON1
.long 0x22080060 @;ROMCON1
.long 0x00000060 @;ROMCON2
.long 0x00000060 @;ROMCON3
.long 0x00000060 @;ROMCON4
.long 0x00000060 @;ROMCON5
.long 0x11004380 @;DRAMCON0
#.long 0x20040380 @;DRAMCON0
.long 0x00000000 @;DRAMCON1
.long 0x00000000 @;DRAMCON2
.long 0x00000000 @;DRAMCON3
.long 0xce278360 @;REFEXTCON

# .long 0x00003E02 @ EXTDBWTH
# .long 0x02000060 @ ROMCOON0 0~0x200000
# .long 0x40010040
# .long 0x00000060
# .long 0x00000060
# .long 0x00000060
# .long 0x00000060
# .long 0x14010301

# .long 0x00000000
# .long 0x00000000
# .long 0x00000000
# .long 0x9C298360

.data
.SPACE 1024
USR_STACK:
.SPACE 512
UDF_STACK:
.SPACE 512
ABT_STACK:
.SPACE 512
IRQ_STACK:
.SPACE 512
FIQ_STACK:
.SPACE 512
SUP_STACK:

4

aeyes wrote on Thursday, August 07, 2008:

Oops please note at the call to the IRQ handler the commands that you see here for saving the registers and restoring them have actually been removed , this is a slightly older script, actually I am expecting that the save and restore context will do the job so I do not need it here I have just retained the SUBS pc, lr, #4 in the IRQ handler routine as I have declared the tick ISR as just a function . That is I have removed the naked and the -attribute - notations .

Regards

5

aeyes wrote on Thursday, August 07, 2008:

Also for this section in the startup script above

.extern ISR_FiqHandler 

STMFD sp!, {r0-r7, lr} 

BL ISR_FiqHandler 

LDMFD sp!, {r0-r7, lr} 

SUBS pc, lr, #4 

Please read it as

.extern vTickISR

BL vTickISR

SUBS pc, lr, #4 

and the finction void vTickISR( void ) __attribute__((naked))

has been changed to void vTickISR( void ) and of course I have cleared the S3C4510 interrupt flag once I got into the function.

Regards

6

aeyes wrote on Thursday, August 07, 2008:

Tried allocating stack space in supervisor mode , still no avail :frowning: … I have to do a stack trace …

7

aeyes wrote on Thursday, August 07, 2008:

Also I altered the order of the makefile and placed the stsrtup code to start fron 0x00000000 , in LPC2106 port the startup code is placed elsewhere . Why was the startup code linked at the end in the case of LPC2106 ?

8

rtel wrote on Thursday, August 07, 2008:

> Also I have edited only the prvsetuptimer function of the
> Also S3C4510b hass a non vectored interrupt structure so I
> have dedicated the IRQ interrupt request for the timer
> interrupt,

When you come to do the real code you can do the save and restore of the context from the single interrupt entry point.  There are examples of doing this in the FreeRTOS.org download.  I think the IAR STR9 demo does this.

Regards.

9

rtel wrote on Thursday, August 07, 2008:

> Also for this section in the startup script above
>
> .extern ISR_FiqHandler 

Are you using the FIQ interrupt?  Best not to do this, at least until you have a simple system up and running.

Regards.

10

rtel wrote on Thursday, August 07, 2008:

You need to setup the linker script to be correct for whatever your processor has configured.  Some processors allow remapping, for example so the vector table can be in RAM. 

Regards.

11

aeyes wrote on Thursday, August 07, 2008:

I have this linker script for the processor

SECTIONS
{
    . = 0x00000000;
    Image_RO_Base = .;
    .text : { *(.text) }
    .rodata : { *(.rodata) }
    Image_RO_Limit = .;
    . = 0x01000000; 
    Image_RW_Base = .;
    .data : { *(.data) }
    Image_RW_Limit = .;
    Image_ZI_Base = .;
    .bss : { *(.bss) }
    Image_ZI_Limit = .;
    end = .;
    .debug_info     0 : { *(.debug_info)  }
     .debug_line        0 : { *(.debug_line)  }
       .debug_abbrev   0 : { *(.debug_abbrev)}
       .debug_frame    0 : { *(.debug_frame) }
}

and this is my makefile which I have referred from the LPC2106 port , I have only changed the sequence of linking of the startup file the interrupt vectors are not remapped in this case .

CC=arm-elf-gcc
OBJCOPY=arm-elf-objcopy
ARCH=arm-elf-ar
CRT0=crt.s
WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare
        -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused

#
# CFLAGS common to both the THUMB and ARM mode builds
#
CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I…/…/Source/include
        -I…/Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT)
         $(OPTIM) -fomit-frame-pointer -fno-strict-aliasing

ifeq ($(USE_THUMB_MODE),YES)
    CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
    THUMB_FLAGS=-mthumb
endif

LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map

RTOS_SOURCE_DIR=…/…/Source
DEMO_SOURCE_DIR=…/Common/Minimal
#
# Source files that can be built to THUMB mode.
#
THUMB_SRC =
hello.c
serial/serial.c
ParTest/ParTest.c
$(DEMO_SOURCE_DIR)/integer.c
$(DEMO_SOURCE_DIR)/flash.c
$(DEMO_SOURCE_DIR)/PollQ.c
$(DEMO_SOURCE_DIR)/comtest.c
$(DEMO_SOURCE_DIR)/flop.c
$(DEMO_SOURCE_DIR)/semtest.c
$(DEMO_SOURCE_DIR)/dynamic.c
$(DEMO_SOURCE_DIR)/BlockQ.c
$(RTOS_SOURCE_DIR)/tasks.c
$(RTOS_SOURCE_DIR)/queue.c
$(RTOS_SOURCE_DIR)/list.c
$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c
$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c

#
# Source files that must be built to ARM mode.
#
ARM_SRC =
$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c
serial/serialISR.c

#
# Define all object files.
#
ARM_OBJ = $(ARM_SRC:.c=.o)
THUMB_OBJ = $(THUMB_SRC:.c=.o)

rtosdemo.hex : rtosdemo.elf
    $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex

rtosdemo.elf :$(CRT0) $(ARM_OBJ) $(THUMB_OBJ) Makefile
    $(CC) $(CFLAGS) -nostartfiles $(CRT0) $(ARM_OBJ) $(THUMB_OBJ)  $(LINKER_FLAGS)

$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
    $(CC) -c -g $(THUMB_FLAGS) $(CFLAGS) $< -o $@

$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
    $(CC) -c -g $(CFLAGS) $< -o $@

clean :
    touch Makefile

I am using the rom_arm.bat to compile … the linker thus shown is working because I have compiled sinpler codes with the same linker and run them.

Here is the batch file from the LPC2106 port where I have altered the linker script file to be my file and stopped the optimisation .

set USE_THUMB_MODE=NO
set DEBUG=
set OPTIM=-O0
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=FLASH.LD
make

12

aeyes wrote on Thursday, August 07, 2008:

No I have left the fiq interrupt as of now I have not touched it , I am working with only the IRQ…