Hardfault on cortex M3

Kernel
1

bertino wrote on Wednesday, May 28, 2014:

Hi,

I’m working on an application that sometimes fails and gets into the HardFaultHandler.

I was trying to find a way to understand the cause by implementing your suggestions in:
http://www.freertos.org/Debugging-Hard-Faults-On-Cortex-M-Microcontrollers.html

but looks like the asm code in your example has a syntax that is not compatible with
IAR Embedded Workbench v7.10, for example the decalration :

static void HardFault_Handler( void ) attribute( ( naked ) );

makes IAR complain for a missing “{”

so since assembly directives are not my bread and butter,
do you have a reference example based on IAR that I can look at to get over this quickly?
Not for lazyness, I actually would like to increment my knowledge on asm but since I have tight deadlines I’m looking for the fast track if there is any suggestion that can help;

Thanks,
Adalberto

2

rtel wrote on Wednesday, May 28, 2014:

The code as posted on the FreeRTOS.org site is using GCC syntax. IAR do a pretty good job of allowing GCC syntax through their compiler, but it looks from your post that the naked attribute is not supported all the same.

There would be a couple of options. First look in the IAR manual to see if they have an equivalent to the naked attribute (which prevents the compiler from inserting any prologue or epilogue code), or second move all the code into an assembly file.

Does your project have any assembly files already? It probably will do for the C start up code and vector table. Somewhere you will have a default HardFault_Handler function, and you would be able to add the assembly code from the web page in that.

If the HardFault_Handler function is a C file and you don’t have any assembler files in your project you will have to create your own assembly file and add it to the project. In IAR syntax it would look something like the following:


    RSEG    CODE:CODE(2)
    thumb

    PUBLIC HardFault_Handler
    EXTERN prvGetRegistersFromStack

HardFault_Handler	

    tst lr, #4
    ite eq
    mrseq r0, msp
    mrsne r0, psp
    ldr r1, [r0, #24]
    ldr r2, prvGetRegistersFromStack
    bx r2
	
	END

Regards,
Richard Barry.