Hard fault problem - Cortex M3

Kernel
1

masio wrote on Monday, September 29, 2014:

Hi. I’m writing a code for LPC1769 (Cortex M3) with FreeRTOS and LPCOpen library. The hard fault occurs when a FreeRTOS API function is called from an ISR.The interrupt has the same priority as the kernel (configKERNEL_INTERRUPT_PRIORITY).

The RTC interrupts make this error.

This function configs the RTC:

void rtc_init(){
Chip_RTC_Init(LPC_RTC);
Chip_RTC_CntIncrIntConfig(LPC_RTC, RTC_AMR_CIIR_IMSEC, ENABLE);
Chip_RTC_ClearIntPending(LPC_RTC, RTC_INT_COUNTER_INCREASE | RTC_INT_ALARM);
NVIC_EnableIRQ((IRQn_Type) RTC_IRQn);
Chip_RTC_Enable(LPC_RTC, ENABLE);
NVIC_SetPriority((IRQn_Type)RTC_IRQn,configKERNEL_INTERRUPT_PRIORITY);
}

IRQ Handler:

<i>
void RTC_IRQHandler(void)
{
	uint32_t sec;

	if (Chip_RTC_GetIntPending(LPC_RTC, RTC_INT_COUNTER_INCREASE)) {
		Chip_RTC_ClearIntPending(LPC_RTC, RTC_INT_COUNTER_INCREASE);
	}

		xSemaphoreGiveFromISR(sem_temp,NULL);    // THIS CAUSES THE ERROR.
	}

}
</i>

FreeRTOSConfig.h file: http://paste.ofcode.org/DEERe56y3X8Eg7tXZgBRHd

Sorry for my bad english.

Thanks!

2

davedoors wrote on Tuesday, September 30, 2014:

NVIC_SetPriority((IRQn_Type)RTC_IRQn,configKERNEL_INTERRUPT_PRIORITY);

That line will not be right if configKERNEL_INTERRUPT_PRIORITY is defined using all 8 bits, as it normally is. NVIC_SetPriority wants the priority specified using just the number of bits implemented by your LPC part. See RTOS for ARM Cortex-M and make sure you are using a recent FreeRTOS version to take advantage of the extra self checking with configASSERT() defined.

3

masio wrote on Monday, October 06, 2014:

Ok I’ll try that. Thanks!