FreeRTOS TCP/IP stack support for XIlinx Ultrascale+ AXI ethernet

Is there any support for FreeRTOS TCP/IP stack support for Xilinix PL side ethernet interface. I found Network interface port layer code for XIlinx ultrascale on FreeRTOS github page. But port included emaclite interface specific code. How to use FreeRTOS TCP/IP stack for PL side ethernet(AXI ethernet interface). What will be a good starting point as i am new in field of driver and HAL development.

Hello @ashutosht! I’m going to check with some folks. I’m not the TCP/IP expert and I don’t want to give you misleading advice. I’ll message back when I have more information.

Hello @ashutosht, FreeRTOS+TCP works well on both the Zynq 7000 (MicroZed / Zybo), as well as on Ultrascale.

I have never worked with “Xilinix PL”, but if you find a working low-level Ethernet driver, we can help you on this forum to get it integrated with FreeRTOS+TCP.

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Xilinx provide support for PL ethernet (ethernet on FPGA card) for LwIP stack. Xilinx also provide port specific code for LwIP stack. Can i use that code as a reference and try to implement network interface port specific code for PL side ethernet in FreeRTOS+TCP??

Yes go ahead, and you can always ask questions in this post. In my experience, the Xilinx libraries are pretty straightforward, so it shouldn’t be too complicated.

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