I am glad to see that I am not the only one who gets confused by ST’s documentation.
Definitely, looking at my own condition, it will be injustice to say that you are the only one. This is one of the reasons, why I wrote previously: to preserve my sanity, I do write some comments and definitions, just to make sure that I am fully functional.
I suppose that you also found : https://community.st.com/s/article/FAQ-DMA-is-not-working-on-STM32H7-devices ?
Honestly, I did. Previously on this very same forum myself had a discussion with someone else too …
It shows this picture:
Yes I am sure that ETH works perfectly when I locate all DMA memories here:
RAM3 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
The missing part: AXI_SRAM != SRAM3
SRAM1 (D2), SRAM2 (D2), SRAM3 (D2), SRAM4 (D3)
while AXI_SRAM (D1)
The different Domains have different clock speeds too …
There is even confusion about the names “RAM3”. Have you seen this:
The memory at 0x24000000 has a size of 512 KB and it is called AXI SRAM
"SRAM3 has a differente address: 0x30040000 with a size of 128 KB.
SRAM3 length = 0x30047fff - 0x30040000 = 0x7fff = 32kB
AXI_SRAM length = 0x2407ffff - 0x24000000 = 0x7ffff = (524,287) 511kB
SRAM3 is always at 0x30040000, the documents anywhere it says, otherwise ?
(I am unable to see that. If so, it would be even more confusion)
Looking at the picture, it is indeed a long way from AXI to ETH, indeed through the D2toD1 AHB bridge.
I do keep myself a small definition comment set to keep myself a bit stable:
The comments from the datasheet itself. I think yesterday night, poring over, I saw on the ST forum also someone having a similar question about abusing the bridge.
The only problem, is when you use it in a real world scenario, when one finds that there seems to be that data at this location not appearing (Just like how you got late to office, due to a traffic congestion. You did appear at work, but you got delayed. But it would be easy for some to think that you did not appear for work!). But alas, that data got blocked on the bus, because there was some data transmitted on the Ethernet. At a later stage, that would be a very weird and hard to fix bug. Someone hops along, complaining to ST, chip is buggy, when I do this, data does not appear in memory, maybe memory has holes or something like that. It would be a painful issue for anyone to get a foothold on to. Better documentation, always does help. But what to do… (You ask for more, maybe they will say tomorrow, we are not going to give you any docs. This issue I had faced many times with driver development for peripherals in another lifetime. My simple prayer is that vendors do things in a positive mindset and not otherwise)
For convenience sake, I add it in here.
* STM32H743 Memory layout
* 0x20000000 - 0x2001FFFF DTCM-RAM <- Stack & Heap @(Size: 0x1ffff = 131071, 128kB)
* 0x20020000 - 0x23FFFFFF Reserved
* 0x24000000 - 0x2407FFFF AXI SRAM <- Current IRAM2 @(Size: 0x7ffff, 524287, 511kB)
* 0x24080000 - 0x2FFFFFFF Reserved
* 0x30000000 - 0x3001FFFF SRAM1 <- (Size: 0x1ffff, 131,071, 128kB)
* 0x30020000 - 0x3003FFFF SRAM2 <- (Size: 0x1ffff, 131,071, 128kB)
* 0x30040000 - 0x30047FFF SRAM3 <- Current Rx/Tx Descriptors, Rx buffers (Size: 32767, 128kB)
* 0x30048000 - 0x37FFFFFF Reserved
* 0x38000000 - 0x3800FFFF SRAM4 <- (Size: 0xffff, 65535, 64kB)
* 0x38010000 - 0x387FFFFF Reserved
* 0x38800000 - 0x38800FFF Backup SRAM <- NVRAM (Size: 0xfff, 4095, 4kB)
* 0x38801000 - 0x3FFFFFFF Reserved
#define DTCM_RAM_beg 0x20000000 /* TCM RAM, for critical data/stk/heap; eg: ISR's */
#define DTCM_RAM_end 0x2001ffff
#define DTCM_RAM_siz 0x1ffff /* 131,071 bytes */
#define D1_SRAM_AXI_beg 0x24000000 /* D1 domain */
#define D1_SRAM_AXI_end 0x2407ffff
#define D1_SRAM_AXI_siz 0x7ffff /* 524,287 bytes */
#define D2_SRAM1_beg 0x30000000 /* D2 domain */
#define D2_SRAM1_end 0x3001ffff
#define D2_SRAM1_siz 0x1ffff /* 131,071 bytes */
#define D2_SRAM2_beg 0x30020000 /* D2 domain */
#define D2_SRAM2_end 0x3003ffff
#define D2_SRAM2_siz 0x1ffff /* 131,071 bytes */
#define D2_SRAM3_beg 0x30040000 /* D2 domain */
#define D2_SRAM3_end 0x30047fff
#define D2_SRAM3_siz 0x07fff /* 32,767 bytes */
#define D3_SRAM4_beg 0x38000000 /* D3 domain */
#define D3_SRAM4_end 0x3800ffff
#define D3_SRAM4_siz 0x0ffff /* 65,535 bytes */
#define SRAM4 (D3_SRAM4_siz + 1)
#define SRAM3 (D2_SRAM3_siz + 1)
#define SRAM2 (D2_SRAM2_siz + 1)
#define SRAM1 (D2_SRAM1_siz + 1)
#define SRAM_AXI (D1_SRAM_AXI_siz + 1)