Hi Heinrich,
Nice to see, you got it booted up well. Cheers!
Had a quick look, saw a small issue.
The linker scripts says this:
RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
From what it “appears to be obvious” to me, RAM_D2 is a sum of D2_SRAM1 (128k), D2_SRAM2 (128k), D2_SRAM3 (32k) 128+128+32 =288k, which looks fine.
But, D2_SRAM1, D2_SRAM2, D2_SRAM3 are all independent, within the D2 domain.
ie, They have their own independent Clocks from AHB2:
If you enable all 3 clocks all the time, identically; Then everything is alright. But if one does think that it is one single memory location, enables only a single clock, this could likely entail long hours of debugging. This could be a pain.
In the belief that, I am looking at it correctly;
I think better would be to have it as 3 separate memories themselves, rather than as a single memory region, which would otherwise cause confusion to someone who is not careful enough ?
(As it is, the H7 is complex enough, making a variation to the documentation would be even more confusing.)
Just my thoughts. I do not want to sound a bit rude and short live your success-happiness moment, but thought that it would be in the best interest of all.
Thanks,
Manu