FreeRTOS-Plus-TCP on SAME70 and latest code

Does anyone have a functional FreeRTOS-Plus-TCP on a SAME70 ??
I’m using the a FreeRTOSIP_config.h I found thru this form but am on the current tip of master for the FreeRTOS-Plus-TCP git repo. The Phy seems to be discovered just fine.
(PhyId: 0x00221560)

I’m not very familiar with DriverSAM driver. It seems like it is never thinks there is a Link. The prvEMACHandlerTask() is just spinning. The GMAC_Handler() never is invoked.

We have the LWIP based network stack working fine on this hardware (It is a custom board) but were trying to decide if the FreeRTOS-Plus-TCP might be a better choice.

A know good FreeRTOSIP_config.h would be be nice to compare against.

Thanks

From your description it doesn’t sound like a configuration file issue. Are the lwIP and +TCP MAC drivers using the sam low level driver libraries? If so, can you step through both in the debugger to see the differences? Especially the part that decides if the link is up or not.

It sounds like you have found the right driver.

It combines the drivers for SAM4E and SAME70.

There is a demo project for SAME70 which uses mentioned driver in a Makefile project.

I’m using the a FreeRTOSIP_config.h

Mind you that the correct name is FreeRTOSIPConfig.h, without an underscore.

@rtel wrote:

Are the lwIP and +TCP MAC drivers using the sam low level driver libraries?

+TCP uses the GMAC driver as it was created by Atmel (Microchip), but with some changes:

  • allow zero-copy sending and receiving
  • several optimisations

Sorry, I miss typed it. I am using FreeRTOSIPConfig.h

In comparing the original ASF3 KSZ8081RNA phy driver and I see the following in ethernet_phy_auto_negotiate():

#if BOARD != SAME70_XPLAINED
/*
* Clock input to XI (Pin 8)
*/
ul_phy_ctrl2 = GMII_RMI_REF_CLK_SELECT;
uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_PCR2, ul_phy_ctrl2);
if (uc_rc != GMAC_OK) {
gmac_enable_management(p_gmac, false);
return uc_rc;
}
#endif

We would be executing this. Not sure why SAME70_XPLAINED doesn’t need it. So I’m going to try and copy this in and try it.

Here’s a difference I noticed with the phy drivers. The ASF3 phy driver had the following definition:

#define GMII_PCR1        0x1E   // PHY Control 1
#define GMII_PCR2        0x1F   // PHY Control 2

In the FreeRTOS-Plus-TCP/portable/NetworkInterface/Common/phyHandling.c :slight_smile:

#define phyREG_19_PHYCR     0x19U /* 25 RW PHY Control Register */
#define phyREG_1F_PHYSPCS   0x1FU /* 31 RW PHY Special Control Status */

Are these referring to the same register ?? Should the 0x19U be 0x1EU ?

You wrote:

Here’s a difference I noticed with the phy drivers.
The ASF3 phy driver had the following definition:

#define GMII_PCR1 0x1E // PHY Control 1
#define GMII_PCR2 0x1F // PHY Control 2

In the FreeRTOS-Plus-TCP/portable/NetworkInterface/Common/phyHandling.c :slight_smile:
#define phyREG_19_PHYCR 0x19U /* 25 RW PHY Control Register */
#define phyREG_1F_PHYSPCS 0x1FU /* 31 RW PHY Special Control Status */

Are these referring to the same register ?? Should the 0x19U be 0x1EU ?

Note that the Atmel driver defines GMII_PCR2, but it does not use it. It defines and is also uses the first register GMII_PCR1.

phyHandler.c also refers to this register here:

pxPhyObject->fnPhyRead( xPhyAddress, 0x1E, &ulControlStatus );

I should have given it a proper name, something like PHY_Control_1, in stead of the number 0x1E. PHY_Control_1 is very specific for this PHY.

The module common/phyHandling.c is a generic PHY-driver. It has also been used and tested on KSZ8081 (E70-Xplained). I just retested it on my SAME70-XPLD board, and it worked fine.
I saw this logging:

[IP-task   ] PHY ID 221560
[IP-task   ] xPhyReset: phyBMCR_RESET 0 ready
[IP-task   ] +TCP: advertise: 01E1 config 3100
[IP-task   ] prvEthernetUpdateConfig: LS mask 00 Force 1
[IP-task   ] Autonego ready: 0000786d: full duplex 100 mbit high status

The PHY-driver creates some logging by calling FreeRTOS_printf(). Can you somehow make this logging visible?

You wrote:

#if BOARD != SAME70_XPLAINED
/*
* Clock input to XI (Pin 8)
*/
ul_phy_ctrl2 = GMII_RMI_REF_CLK_SELECT;
uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_PCR2, ul_phy_ctrl2);
if (uc_rc != GMAC_OK) {
gmac_enable_management(p_gmac, false);
return uc_rc;
}
#endif

I do not have this code. Both my SAME70 and SAM4E projects use the generic PHY driver.
It looks like this is part of Atmel’s PHY driver, which you do not need if you are using phyHandling.c