FreeRTOS on cortex M1

val54321 wrote on Tuesday, January 06, 2009:

I haven’t been able to find any information on cortex M1 and FreeRTOS.  Is there support? If not, is there any plan to support?
Thanks for you help, I appreciate it.  Val

edwards3 wrote on Tuesday, January 06, 2009:

I would be interested in M1 too. How similar to the M3 is it?

iammrt wrote on Tuesday, November 24, 2009:

I was about to writte a Cortex-M1 Port, but as it seems the documentation of FreeRTOS is pretty poor! I cant find anything about ISR related things. Does a TimerTick and a Context switch is enough? What does freeRtos need? How i ContextSwitch and how is the timertick bound to the OS. Its not so hard to port such a tiny OS, but its pretty though if you dont have a documentation giving a clue.

Im disappointed here… They only refer to their expensive ebooks. But i have no idea if those books are more detailed as this poor documentation on the website.

Where to find a detailed documentation about systemfunktions, where to find a port-how-to can anyone help me pls?

davedoors wrote on Tuesday, November 24, 2009:

The source code is the best documentation. There are 23 architectures supported, each one is implemented differently. The book is a users guide, not a porters guide and there is a TOC available on the WEB site.

iammrt wrote on Tuesday, November 24, 2009:

So where to find  the porters guide? Per example I’m pretty sure FreeRTOS needs an “SysTick” from any clock. Which function need to be called?! I think in theory it’s like


Same goes for Context Switches and critical code section. Needs the ContextSwitch to call the scheduler for rescheduling? Where i can find this information?

It shouldnt be so hard to port the OS to another type of Microcontroller.

I had a look into other ports (for different controllers) and i found the most code poor or not commented. :frowning:

Maybe i just dont find the correct link on the website, would you mind to provide me the link? :o)

davedoors wrote on Tuesday, November 24, 2009:

This page provides basic information on how to setup the directory structure and which files are needed

As far as the actual port goes, that is completely dependent on the architecture. Each architecture behaves differently and provides different features.

Yes you need a tick interrupt and from there you call vTaskIncrementTick() and vTaskSwitchContext(), just look at any of the other ports, they all do this.

As to how hard it is, some are easier than others, it depends on your own knowledge and experience how hard it will be.


iammrt wrote on Tuesday, November 24, 2009:

Thanks for advice, gonna try my luck. :slight_smile:

iammrt wrote on Wednesday, November 25, 2009:

Okay a summary of how i think its been done. (Pseudocode)

This shut work for all architectures.

  Flag a Context switch;
  sysCall -> vTaskIncrementTick();

  get location of current TCB;
  Save registers;
  Put new StackTop into TCB;
  sysCall -> vTaskSwitchContext();
  Restore the context
  set new stacktop
  Pop registers

Is this correct?

iammrt wrote on Thursday, November 26, 2009:

Come on please response.
I also need a Function or a Variable that tells me which task will be working next. I mean scheduler should write an array with pointer to the next Task that will be run or so. I cant see the border between Port-Code and Kernel.
Where is a documentation about this? Im sure im only to dump to find it. I crawled whole homepage, all i can find is a “port-guide” that teaches my how to set up folder structure. But thats not the essentials i want to know.

If someone know where to find this documentation buy-able / or free, let me know please.

rtel wrote on Thursday, November 26, 2009:

> Come on please response.

FreeRTOS is the result of 6 years work which is provided to you absolutely free.  (practically) Nothing is asked in return.  So my first piece of advice for you is, if you want help, don’t start off by complaining about how terrible everything is.  If you want me to write a port for you I’m happy to send you a quote.

Its not perfect, but it is as good as some commercial offerings, and better supported too.  It is used successfully by thousands of people all around the world.  Most people do not try and write a port from scratch, although hundreds do, quite successfully.  This is an open source project, the idea being, instead of demanding more for free, you say, thanks for what I have got, how can I contribute back?

> I also need a Function or a Variable that tells me which task will be working
> next.


> I mean scheduler should write an array with pointer to the next Task that
> will be run or so.

Why?  I don’t know of any system that does this.  How is it going to know which is going to run next, it cannot predict which events are going to occur in its environment.  It only knows which should be running now.

> I cant see the border between Port-Code and Kernel.

As explained in the readme files in each directory, and as explained here:

Plus I think the quick start videos talk through the directory structure, although I cannot remember.

+ FreeRTOS/Source -> Core source code
+ FreeRTOS/Source/Portable -> Implementation of the port layer
+ FreeRTOS/Source/include/portable.h -> effectively the interface


iammrt wrote on Thursday, November 26, 2009:

It is not my intention to be rude! Sorry if this sounds like.

I just want to write a port for the Cortex-M1. I did it for some other RTOS already. I’m student in cybernetics and want to learn, want to figure out which RTOS are out there and want to understand how they work.
I would be glad to write a port and submit it to the community. I just find the documentation about the interface of port(HW related) and Kernel isn’t clear.

I don’t want you to ask to write a port for me, i want to understand how its done for this OS and do it by myself. I only ask for a documentation about it. If you say “no there is none” its okay, i try to figure it out myself - write a docu and the port. But i think this is the tough way.

I respect your work. And I’m a big fan of openSource software and projects.

And from my last post.
When a ContextSW occures, scheduler needs to provide a hint which task will come up now (re-scheduling) in any form. So the new Task can be loaded to the TCB. Maybe i don’t understand the idea of the freeRTOS scheduler, but that is how the other RTOS  i worked with did.

Once again, I don’t want to be rude, I’m just curious.

davedoors wrote on Thursday, November 26, 2009:

pxCurrentTCB points to the task control block of the currently running task. In the tick interrupt, or when a task yields or blocks, vTaskSwitchContext() is called and this sets pxCurrentTCB to a new (or maybe the same) TCB.

Look at the tick interrupt handler for any of the many existing ports and you will see they all call vTaskIncrementTick() then vTaskSwitchContext(). Just copy that. The clever bit is the actual switching, which is different for every architecture so cannot be documented in one place. The user manual for the architecture you are using (M1 in this case) gives the information needed.

iammrt wrote on Thursday, November 26, 2009:

Ah I see this brings clarification. So after vTaskSwitchContext() has been finished the pxCurrentTCB points to the new scheduled TCB. And i can set it up so.
Thanks for your patience!

iammrt wrote on Thursday, December 17, 2009:

I finished my Cortex M1 Port allready. I’ll adept my code to the conventions of FreeRtos. Using of specified variable names and so.
Wasnt able to find a documentation about the conventions, and what a port need to full-fill to get added to the repository.
Since there is no interface description (kernel < > port) i can offer the one I figured out. Well would need to adept it to freeRtos conventions as well.
The Context Switch is working. I tried out inter-task communication, it worked. Scheduler is working as well.

Since there is no interface description available on web (kernel < > port) i can offer the one I figured out. Well would need to adept it to freeRtos conventions as well.

So what I need to do now? Where to send the port and what are the conventions to get a port added to the project.


kpettit1 wrote on Friday, May 21, 2010:

I realize this thread is rather old, but I was curious about the Cortex-M1 port as I had written a port back in November 2009 also and have it running on an Actel FPGA.  Which device were you running the Cortex-M1 on?  Did that implementation of the processor include support for software interrupts?  The Actel version did not which made support for deferring a task early (forcing a context switch) a bit tricky.  

I ended up having to add an external interrupt controller to the Cortex-M1 and using one of it’s 8 interrupt lines to perform “software interrupts”.  This caused a bit of an issue trying to manage timer tick interrupts, soft interrupts and actual hardware interrupts all using  single interrupt to the processor.  How did you take care of this in your port? 


iammrt wrote on Friday, May 21, 2010:

Hey Ken,

I used the M1A3PL Eval board from Actel with an ProASIC3 FPGA with a M1 running on/in it. Since the Cortex-M1 IP from actel only supports 1 Interrupt line (ya seriously…) i used to add an external interrupt controller aswell.
I actually not remember if I implemented the softinterrupt on the external controller or the M1 itself. The Cortex-M1 NVIC got the possibility to use Softwareinterrupts by raising a flag in a specific register. So the implementation had 1 interrupt line, and it was possible to trigger a S/W Interrupt on this line, but on this line is the external controller aswell so i choose to use the controller for S/W Interrupts.

Well using an external interrupt controller isn’t so elegant, but it works and you have no other option here. At least you will need to write one “big” ISR for the Interrupt line on the Cortex where the external controll is connected to. When a interrupt arrives this ISR needs to determine from which source connected to the external controll the interrupt comes. This is done by reading the external interrupt controllers Status register. By using bit-maskes this is easy. It’s even no problem if 2 Interrupts “stick” at the same time, or just before you had the chance to process the first. Since when this happens you will have both flags for those 2 sources raised on the status register.
What ever this way will never be so fast as multiple interrupt lines on the cpu, mapped through a vector-tabel, can be.

By the way i had some contact with Actel developer because there where a bug in the external interrupt controller IP core. What ever, they told me there should be a new release of cortex-m1 at the begin of 2010. Till now there released nothing new… I was promissed “OS-Support will be enabled so you have the option to use multiple Stack Pointer and all of the Interrupt lines.”

If you don’t need a CPU running in a FPGA and want to use the cortex series, use the M3 (formor ARMv7). Better performance and more functions (fully implemented).


Cheers, I AM MR. T

kpettit1 wrote on Friday, May 21, 2010:

Hey Mr T,

Thanks for the quick response! :) 

Yeah, now that you mention the internal software interrupt bit in the CM1, I seem to recall trying to get that to work also, but I kept getting DATA ABORT when I tried to trigger the soft interrupt.  I think the implementation of the Cortex-M1 on the Igloo AGL600 had an issue there or something.  Since I was / am using this system as more of a prototype, I settled for the external interrupt option.  As I mentioned, it was a bit tricky because I had to add extra logic to manage timer based preemption and portYEILD from the the same interrupt source.   I don’t think I ever encountered the bug in the external interrupt controller, although I was seeing some strange behavior on the SPI controller attached to it.  Hmmm…. wonder if that could have been the problem.  I’ll have to go back an look.  And yes, OS-Support would have been nice.  In fact, I checked for updated just a few days ago hoping maybe they had added this, but no luck.

I was using the Actel M1AGL Eval board mainly just because I had it lying around and knew I could add whatever custom hardware I needed.  It’s kinda nice having the 1M RAM and 16M Flash (on the eval board) for development purposes.  My plan was always to migrate to an Atmel AT91SAM7X512 part at some point.  I’m pretty sure I saw that FreeRTOS had been ported to that device.

Thanks again.  And thanks Richard Barry (and others?) for FreeRTOS!  Really nice package.

rtel wrote on Friday, May 21, 2010:

Actel now have some nice FreeRTOS info on their web site, thanks to their port to the Cortex-M3 based Smart Fusion device.  I have therefore added an Actel forum in the FreeRTOS interactive site.  I would therefore invite you to post your M1 code and any documentation you can provide (what works, doesn’t work, which hardware it runs on, etc.) there too.


kpettit1 wrote on Friday, May 21, 2010:

Hey Richard,

Sure, be glad to upload the port.  I was just looking at my changes to the baseline Actel Cortex-M1 example that came with their eval kit and I believe the baseline example should be capable of running the port directly.  I created the port using GCC and a managed Eclipse project, so it currently doesn’t follow the directory structure exactly, but its close.  Also, I need to write some documentation regarding the optimization settings.  The GCC compiler creates different stack frames based on the optimization level, and the port.c file is currently written to support -O0 only.

I will work on some documentation regarding the port and the hardware requirements and post it.  Given that this is an FPGA eval based platform, I doubt many (if any) will find it all that useful, although you never know I guess.

How do you manage “updates” in the unsupported ports section (in case I add additional support later, for instance)?


rtel wrote on Saturday, May 22, 2010:

How do you manage “updates” in the unsupported ports section (in case I add additional support later, for instance)?

I can add extra attachments to posts, and replace attachments to posts, but I’m not sure if that is just because I am an administrator.  Other than that comments and new threads can be created.