FreeRTOS Demo for HiFive1: write to read-only address

In the RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio demo example, main.c uses the following PLIC addresses (lines 67 and 68).

#define mainPLIC_PENDING_0 ( * ( ( volatile uint32_t * ) 0x0C001000UL ) )
#define mainPLIC_PENDING_1 ( * ( ( volatile uint32_t * ) 0x0C001004UL ) )

In lines 145 and 146, there is a write access.

/* Clear all pending interrupts. */

However, the addresses are read only, see page 45 in SiFive FE310-G002 Manual v19p04, and should be used different.

I would appreciate if someone could take a look.


Thanks for pointing this out, I also read the correct way:

“A pending bit in the PLIC core can be cleared by setting the associated enable bit then performing a claim as described in Section 10.7.”

The PR can be found here. Thanks.