I am using FreeRTOS 8.2.1 on a TI AM4379 using the Cortex A9 port.
All is well, I have 6 tasks running, interrupts are working…
Until I enable the L1 cache, at which point I start getting interrupt 1023 being fired (‘spurious interrupt’ according to ARM docs). Sometimes I get the expected interrupts (timer, ethernet packet rx etc) followed immediately by an int 1023, sometimes I only get an int 1023 (and don’t receive the interrupt I was expecting).
The problem only occurs when the MMU is flagging the DDR3 RAM area (from which the code is running) as WriteBack, WriteAllocate (the ‘fastest’ setting). Using WriteThrough, NoWriteAllocate (slower) and the problem goes away. This led me to suspect a timing issue in the FreeRTOS Cortex A9 interrupt handler (maybe writing the IAR and re-enabling interrupts before the write had time to clear the int) but I can’t find anything suspect in there.
I noticed that the FreeRTOS Cortex A9 int handler doesn’t write the Priority Mask Register (PMR), and so doesn’t support nested interrupts. I believe this could potentially cause a 1023, if interrupts are re-enabled in the handler before the interrupt source has been cleared, and the PMR hasn’t been updated with the value of the current int priority, so the same interrupt would be triggered again (interrupting itself, thus the 1023). It looked like this may be possible in the FreeRTOS int handler, as interrupts are enabled just before the OEI register is written, but swapping the int enable and int clear didn’t solve the problem.
Not sure what else to try! I need to enable the L1 cache for performance reasons.
Is anyone using FreeRTOS on a Cortex A9 WITH L1 cache enabled (WriteBack, WriteAllocate)? Has anyone experienced similar problems and found a solution??!
Many thanks and best regards,