I think I have found a possible problem in the following LPC2xxx port.c files
In all cases the VIC interrupt is enabled before the address of the vector is set. By default the address registers are 0, so if an interrupt is pending the processor will jump to location 0.
Also in some cases the VICIntEnable register is or equalled and in some cases just set. This should not matter, other than the wasted cycles.
from the GCC lpc32xx port.c
VICIntEnable = 0x00000010;
/* The ISR installed depends on whether the preemptive or cooperative
scheduler is being used. */
#if configUSE_PREEMPTION == 1
extern void ( vPreemptiveTick )( void );
VICVectAddr4 = ( portLONG ) vPreemptiveTick;
extern void ( vNonPreemptiveTick )( void );
VICVectAddr4 = ( portLONG ) vNonPreemptiveTick;
VICVectCntl4 = 1;
Really the VIC interrupt should be disabled first, the address then set and finally the interrupt enabled.