In all cases the VIC interrupt is enabled before the address of the vector is set. By default the address registers are 0, so if an interrupt is pending the processor will jump to location 0.
Also in some cases the VICIntEnable register is or equalled and in some cases just set. This should not matter, other than the wasted cycles.
from the GCC lpc32xx port.c
VICIntEnable = 0x00000010;
/* The ISR installed depends on whether the preemptive or cooperative
scheduler is being used. */
#if configUSE_PREEMPTION == 1
{
extern void ( vPreemptiveTick )( void );
VICVectAddr4 = ( portLONG ) vPreemptiveTick;
}
#else
{
extern void ( vNonPreemptiveTick )( void );
VICVectAddr4 = ( portLONG ) vNonPreemptiveTick;
}
#endif
VICVectCntl4 = 1;
Really the VIC interrupt should be disabled first, the address then set and finally the interrupt enabled.
Thanks for taking the time to report this potential problem.
Interrupts are disabled in the CPSR within tasks.c, immediately prior to the port layer being called to start the scheduler, after which the code you highlight is executed. Therefore interrupts are disabled when the code you highlight is executed.
Does that satisfy you that the problem does not actually exist - or am I missing something?
As you say interrupts should be disabled so it shouldn’t be a problem.
It just that I am having some problems currently that I haven’t got to the bottom of yet. One problems was where I was enabling the VIC interrupt before setting the address, so I did a search of the project tree to make sure there were no other instances and found the port.c file.
I am just being picky, have seen to much code where conditions were incorrectly assumed and get fussy about things.