I am using the ZynqMP SoC, which has a FreeRTOS port based on the FreeRTOS kernel version 10.4.3.
It comes with the HelloWorld_FreeRTOS example, which run fine when loaded and executed directly from QSPI or eMMC.
However, our application use case requires loading it through U-boot. This necessitates configuring the HelloWorld_FreeRTOS example as a “hypervisor guest” through the Xilinx IDE, which modifies the following source code-defined values:
FreeRTOSConfig.h
1) #define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET from 0x10000 to 0x1000
xparameters.h
1) #define XPAR_PSU_ACPU_GIC_BASEADDR from 0xF9020000 to 0x03002000
2) #define XPAR_PSU_ACPU_GIC_HIGHADDR from 0xF9020FFF to 0x03002FFF
3) #define XPAR_PSU_ACPU_GIC_DIST_BASEADDR from 0xF9010000 to 0x03001000
When the HelloWorld_FreeRTOS application is loaded and executed from U-Boot, an exception occurs with the following error:
Assert failed in file port.c, line 513
Below is the extracted function where the issue occurs:
It seems that once vTaskStartScheduler() is called, an exception is triggered.
Does anyone have insights on how to pinpoint and debug this GIC-related issue?
Thanks for your help.
Seems like ICCBPR is not set to a correct value. Does U-Boot change this register before starting the application? I’d also recommend to reach out to Xilinx.
I tried to debug further by adding debug print in the HelloWord_FreeRTOS application just before the exception line in port.c.
For HelloWord_FreeRTOS run on QSPI or eMMC, portICCBPR_BINARY_POINT_REGISTER is readout as 0x2.
However, the build with “hypervisor_guest” enabled and loading from u-boot has the register readout as DEADBEEF.
It seen to me that it is unable to access the GIC register or has no access right or the memory address is incorrect.
Question:
Is there any restrictions on GIC register access based on the current Exception Level (EL) of the processor?
Notice, there is a change in the value of configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET in file FreeRTOSConfig.h being defined under the 2 difference cases. How is the value being determined?
At the meantime, my colleague is also reaching out to Xilinx for their support.
