CycloneV IRQ SVC question

Kernel
1

I am working on the CycloneV and used the demo code as my basis. We are trying to upgrade to the latest DS-5 GCC tools but we are a couple versions back. To get the FreeRTOS_IRQ_Handler to function at all I had to comment out
/* CPS #SVC_MODE /
and
/ CPS #IRQ_MODE */

I don’t see any setup in the CycloneV demo for SuperVisor mode (SVC). Perhaps something is done in the newer versions of GCC that I don’t have yet. Anyone have any experience with CycloneV and dealing with SVC setup? I plan to look through the other Demo ports to see what I can find. Any information would be appreciated.
Thanks
Rick

2

If it is not done in the C code then I expect it will be done in the C startup code supposed with your tools or hardware - by which I mean the code that runs between the system booting and main() being called. Can you find the entry point in your code, then step through that (it will be assembly code) to see where it sets up the different processor modes and stacks? If necessary start a debug session with ‘break on entry’ set (instead of ‘run to main’) to see what executes before main() is called.