Cortex R5F Peripheral Base Address

I’m investigating using traceanalyzer with the Cortex R5F processors on the TI Jacinto platform. Does anyone know where to find the Peripheral base address required to configure the hardware port to enable the analyser to access the counter registers?

Currently I’m finding the comment in trcHardwarePort.h ‘but should work with all Cortex-A and R processors assuming that TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS is set accordingly.’ to be somewhat misleading.
As far as I can private timer of the A9 referred to by the registers does not exist in the Cortex-R processors.

You might be correct about the comment that might be a little bit misleading. I am not familiar with this TI platform so I can’t provide details to implement the HW port for it. But in general, there are two things that must be done.
First, you need a time source, normally a hardware timer. The below defines should be configured:
#define TRC_HWTC_TYPE
#define TRC_HWTC_COUNT
#define TRC_HWTC_PERIOD
#define TRC_HWTC_DIVISOR
#define TRC_HWTC_FREQ_HZ
Second is the critical sections. There are a few HW ports for Cortex-A9 and Cortex-R5 that use the same implementation of the critical section. So maybe it can be reused.

There is a blog post with some more details here:

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Thanks Kristoffer. That clarifies the situation. I think the TI PDK and documentation provide all the required information, with the possible exception of the divisor/prescaler.