rtel wrote on Monday, December 16, 2013:
Thanks Erich - I really should link to that.
Richard - note the ability to manage time when the tick is stopped is built into the RTOS core source files itself, but actually managing clocks when the tick is stopped always requires some porting to specific chips. In other words, the port layer uses the functionality built into the core code to enable tickless operation. So while the FreeRTOS download does not provide an example ‘off the shelf’ (although Erich does) you can add tickless operation to almost any port with a little effort.
There are two ways of doing this. The first is to provide a generic implementation that does whatever the M0+ core allows you to do - but that will always be limited in effectiveness because the core is just the core, whereas power is consumed by peripherals, and because the clocks used to keep the timer counting in the core will stop if you sleep too deeply. Therefore for optimal low power you have to look outside of the core and into the IP the chip vendor (Freescale in your case) have provided for you. You should find the FreeRTOS implementation allows you to override the default timer configuration so you can provide your own, which will optimally be from a very slow (32KHz is popular) 32-bit timer that keeps running even when the clock feeding the M0+ core is off. There are three such examples of this type of optimisation on the FreeRTOS website (actually there are two, but another in SVN which will be on the website soon), and presumably Erich’s provides another example that is happily specific to your selected chip.