Cortex A9 port: The access to portICCPMR_PRIORITY_MASK_REGISTER causes data abort

stephenwwu wrote on Monday, March 24, 2014:

I am porting FreeRTOS 8.0.0 to other ARMv7 platforms based on the …/portable/GCC/ARM_CA9. I found the system generates data abort when accessing portICCPMR_PRIORITY_MASK_REGISTER.

portICCPMR_PRIORITY_MASK_REGISTER is defined as ( *( ( volatile uint8_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) in portmacro.h. According to ARM IHI0048B GIC Architecture Specification, section 4.1.4, all registers support 32-bit access. Some registers support 8-bit access. All other accesses are implementation dependent.

I changed portICCPMR_PRIORITY_MASK_REGISTER to 32-bit wide register, the data abort goes away.

Does the register width change make sense?
Is there any side effect of the width change?

rtel wrote on Monday, March 24, 2014:

To be honest, I’m not sure.

The ICCPMR register is a 32-bit register, but only the least significant byte is implemented. The other three bytes are “Reserved”, and should be read as zero with writes ignored. Therefore I would not have thought it made any difference, but evidently it does. I think you would have to look at the assembly code generated to work out what the problem is.

Please report back what you find.

Out of interest, which chip are you porting to?


stephenwwu wrote on Tuesday, March 25, 2014:

The assembly code was 8-bit load ‘ldrb’ when it is declared as (uint8_t *). The ldrb instruction causes data abort. After changing the definition to (uint32_t *), the assembly code becomes ‘ldr’. No more data abort.

rtel wrote on Tuesday, March 25, 2014:

I have updated all 3 Cortex-A port layers to ensure only 32-bit accesses are made to both the ICCPMR and ICCRPR registers.


stephenwwu wrote on Tuesday, March 25, 2014:

Thanks for the confirmation.