I want to report that the same problem is present in Percepio View 4.10.3 since the TCB retrieval on the traced core is performed by calling pxCurrentTCB (i.e. xTaskGetCurrentTaskHandle()). I am working with multiple cores so I have defined TRC_CFG_RECORDER_MODE as TRC_RECORDER_MODE_STREAMING inside trcKernelPortConfig.h. With this configuration, the FreeRTOS trace macros are defined inside trcKernelPort.h, starting at line 1952. I do not know the exact number of macros that can replicate the problem but traceTASK_SWITCHED_IN() is surely one of them. Using the code reported above prevents the issue.
I have contacted ARM about the original question of this post and they confirmed that there is no architectural constraint to disable interrupts before modifying the ICC_PMR when a Cortex-A9 is paired with a GICv1 (or GICv2), like in my case, so I could definitely solve the problem on my end by not disabling the interrupts. However, I know this is only one of the possible SoC configurations so it is not feasible to do so in general.