Can an interrupt with the same priority as `configKERNEL_INTERRUPT_PRIORITY` cause a Hardfault INVPC?

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1

FreeRTOS Kernel V10.0.0
MCU: nRF52840 SDK 17.1.0

Our device is fully functional, and we are currently performing various tests. During long-term testing, we found that the device occasionally resets, though very rarely — about once every two weeks. We recently confirmed that these resets are due to a Hardfault INVPC.

Upon investigation, we found that configKERNEL_INTERRUPT_PRIORITY was not set to the lowest value (0x7 or higher), but instead was configured to the same value (0x6) as other interrupts.

When we increased configKERNEL_INTERRUPT_PRIORITY to 5, a Hardfault INVPC occurred immediately, and the PC and LR values matched those of the original Hardfault observed in our device.

To verify whether the issue was caused by overlapping kernel and other interrupts, we artificially triggered a PendSV by adding SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; inside the GPIO interrupt handler. However, no Hardfault INVPC occurred during this test.

We are nearing the product launch and would like to resolve this issue.

Q1: Can a Hardfault INVPC occur if an interrupt with the same priority as configKERNEL_INTERRUPT_PRIORITY is triggered?

Q2: How can we intentionally cause a Hardfault INVPC by using an interrupt with the same priority as configKERNEL_INTERRUPT_PRIORITY? What should the code look like?

Additional Hardfault Information:

CFSR: 0x00040000
PC: prvProcessTimerOrBlockTask() → portYIELD_WITHIN_API()
LR: End of xTaskResumeAll()
MSP: 0x2003fef8
PSP: 0x20032348 (same as p_stackaddress)

Thank you in advance for your help.

2

I just confirmed that the PWM interrupt priority (0x7) was lower than configKERNEL_INTERRUPT_PRIORITY (0x6), and this seems to have been the issue. We are planning to change configKERNEL_INTERRUPT_PRIORITY to 0x7. Would it still be a problem if there are interrupts with the same priority as configKERNEL_INTERRUPT_PRIORITY? Or should we change the PWM interrupt to 0x6 as well?

3

Good catch and agreed this is a good fix.

That’s no problem. You can have other interrupts at the same lowest interrupt priority.

I assume that the interrupt priorities you are sharing (0x7 and 0x6) are the unshifted priorities. Where configKERNEL_INTERRUPT_PRIORITY is defined in FreeRTOSConfig.h, the value 0x7 should be shifted left 5 positions (since your MCU implements only 3 priority bits).

4

configKERNEL_INTERRUPT_PRIORITY must be set to the lowest priority. Assuming that your device implements 3 bits for interrupt priroity, this is the correct value (ensure to shift the bits as @jefftenney mentioned). Because this is always needed to be set to lowest possible priority, we have removed the use of this constant in the the later kernel versions.

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