Assessment of the difficulty in porting CPU architecture for freeRTOS

Hello everyone! I am working on implementing a tool to assess the complexity of CPU architecture porting. It primarily focuses on RISC-V architecture porting. As part of my dataset, I have collected the freeRTOS-Kernel project. I would like to gather community opinions to support my assessment. I appreciate your help and response! Based on scanning tools, the porting complexity is determined to be moderate, with a moderate amount of code related to the CPU architecture in the project. It would require a professional team, but not a large-scale one, to handle this task (referring to the overall workload from adapting the project to a specific architecture to achieving full functionality on that architecture). Is this assessment accurate? I look forward to your help and response.

“moderate” is a very subjective term, so it’s hard to say. RISC-V is easier than a MIPS, and harder than a Cortex-M, so if “moderate” is not an extreme one way or the other, then it might be accurate. Compare the amount of code in the MIPS port, where pushing and popping registers and interrupt nesting is all done manually using register relative addressing, to that of the Cortex-M port, which pushes many registers itself, has push multiple instructions, and automatically switches stacks…