Is there any plan of such RXv3 port layer? If so, is there any rough schedule? Because…
Recently Renesas ships new RX MCUs which have new RXv3 CPU core. Some of them, RX72M, RX72N and RX66N, have a double precision FPU (DPFPU) and this DPFPU has dedicated data registers and controle registers. I think that these dedicated registers have to be saved/restored in the task switching sequence but the RXv2 port layer, of course, does not take care of them.
RX Family RXv3 Instruction Set Architecture User’s Manual: Software
Page 38 / 396
1.10 Double-Precision Floating-Point Coprocessor
Last week I started the following Japanese thread regarding to this issue. But now I think that asking you about any plan of new port layer supporting the DPFPU is better to know than not asking, regardless of whether proceeding the thread or not. And I’d like to post a report about your answer to the thread.
A consideration of developing a FreeRTOS kernel RXv3-DPFPU port layer (Please note that original title and all contents are Japanese.)