2x timer period by using system timer

Kernel
1

Hi,

I am using the freeRTOS on iMX8 ARM Cortex M4 and created a simple program to test the system timer.

The code for timer:

mTimer = xTimerCreate("timer", pdMS_TO_TICKS(3000U), pdTRUE, 0, timerCallback);
xTimerStart(mTimer, 0);

The timer period is measured by toggling a pin with digital analyzer. So the program just has code for init, timer and GPIO. I have set the timer for 3 sec, but the measured period is 6 sec. The situation for other values is same, the actual period is always twice as long as the set time.

I have checked the following parameters:

configCPU_CLOCK_HZ  = 264 MHz;
configTICK_RATE_HZ  = 1000 Hz;

and the tick count is increased by 3000 in one cycle, it is also correct. That means that each tick does not have a period of 1ms, even though the value of configTICK_RATE_HZ is set to 1000 Hz. Is there anything else I should check?

Any advise and tips are welcome.

2

Some SWAGs as I haven’t used that port:

  • First, make sure you CPU clock rate is correct for how you have configured the processor.
  • Often, there is a second parameter for the clock rate for the system timer, which is often a scaled form of the cpu clock. Make sure it is right.

Either of these being wrong may cause the port layer to program the tick rate to be off. The best way to confirm that is to use a tick hook to toggle a pin, my guess is that it is running at one half the speed it should be.

3

In addition to Richard D’s post, there is a separate parameter configSYSTICK_CLOCK_HZ in case the systick timer (which, by default, generates the tick interrupt) is scaled from the main CPU clock https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/master/portable/GCC/ARM_CM4F/port.c#L40

4

Just a thought, you are measuring the period correctly? 3 second period timer toggling a pin would give a 6 second period square wave. It’s an easy mistake to make if using a scope to measure.

6

Thanks for all the replies. I have checked the parameter configSYSTICK_CLOCK_HZ in port.c.

In port.c:

#ifndef configSYSTICK_CLOCK_HZ
    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
    /* Ensure the SysTick is clocked at the same frequency as the core. */
    #define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
#else
    /* The way the SysTick is clocked is not modified in case it is not the same as the core. */
    #define portNVIC_SYSTICK_CLK_BIT	( 0 )
#endif

And the configCPU_CLOCK_HZ is defined in FreeRTOSConfig.h:

#define configCPU_CLOCK_HZ        (SystemCoreClock)

In system_MIMX8QX6_cm4.c and system_MIMX8QX6_cm4.h:

#define DEFAULT_SYSTEM_CLOCK      264000000u     
uint32_t SystemCoreClock    =     DEFAULT_SYSTEM_CLOCK;

If above mentioned definitions work correctly, the value of configSYSTICK_CLOCK_HZ in port.c should be 264000000u, but the actual value by debugging is 536742401 (0x2000 1DCD). I changed the definition of configCPU_CLOCK_HZ in FreeRTOSConfig.h to

#define configCPU_CLOCK_HZ        (264000000u)

then the value of configSYSTICK_CLOCK_HZ in port.c is correct. The timer period is also correct. But I still don’t know why the value of configSYSTICK_CLOCK_HZ is false. Is there something that I can read on?

7

It appears that SystemCoreClock isn’t right. Or perhaps its not right and the right time. From your post, I think when you built your code with configSYSTICK_CLOCK_HZ as an alias for SystemCoreClock, it had a value of 536742401. That value isn’t right for SystemCoreClock.

Can you put a data breakpoint on that variable to see who is writing to it and when?

8

After configuring the clocks (before any FreeRTOS calls) you should call

SystemCoreClockUpdate();

9

@RealtimeRik @jefftenney
yes, you are right. I am using the FreeRTOS with another framework. The framework generates the main function automatically. And this main function will just create the main task and call vTaskStartScheduler(). The initialization of board, like SystemCoreClockUpdate() is in the task execution. So the configSYSTICK_CLOCK_HZ is not set correctly. I’ll keep looking for a workaround to use this framework. Thanks for your replies.

10

You REALLY want to initialize as much as possible before bringing up FreeRTOS (at least what can be done without needing interrupts or significant timeouts). I try to create all my tasks, queues, semaphores, etc before I bring FreeRTOS up, as this simplifies a lot of logic on race conditions.

You ABSOLUTELY need to have the processor fully initialized before starting FreeRTOS. You can do stuff like changing clock rates after, but you need to reset EVERYTHING that set itself up based on that clock rate.

11

A warning on configSYSTICK_CLOCK_HZ. Best not to define it yourself unless you really need it – and it doesn’t look like you need it. If you define it yourself, you’ll trigger a config change in the SysTick which could further complicate things for you (CLKSOURCE bit gets cleared in the control register). On the other hand, if you simply let FreeRTOS define it (in the port.c code you posted), you’ll get the normal SysTick config (CLKSOURCE bit set).

Calling SystemCoreClockUpdate() before vTaskStartScheduler() should probably clear things up for you. But if your framework makes that too difficult, then you should be able to call SystemCoreClockUpdate() from your own task code and then call vPortSetupTimerInterrupt() with interrupts masked. Then start your other tasks.

13

I have chosen to call vPortSetupTimerInterrupt() in the task code for now, but will eventually put the corresponding initialization out of the task. Thanks for your tip.

14

I would be VERY careful you understand what you are doing here. Setting up the timer interrupt AFTER enabling the scheduler and the system interrupt structure sounds to me like a very bad idea and subject to creating a timing race. Since the call to vPortSetupTimerInterrupt() is part of the FreeRTOS kernel, you obviously aren’t afraid of editing ‘system’ files, so it shouldn’t be that hard to modify the framework (which seems to be doing something VERY strange to not fully init the CPU as its first thing) to do the initializations before the scheduler is started, or at least to add the system initialization to the schedule startup routine before (or as part of) vPortSetupTickInterrupt().

15

Great point Richard – I did not mean to imply that mya should remove the kernel’s call to vPortSetupTimerInterrupt(). Merely that they could add an application call to that function, much like you might do after changing the core clock speed in the application. Any concerns about the application calling that function?

There is one thing about this thread that still troubles me – how SystemCoreClock ever gets set to anything other than 264000000u. Based on this:

and on the fact that no execution of SystemCoreClockUpdate() could ever set SystemCoreClock to 536742401. Yet the OP has strong evidence SystemCoreClock was set to that value.

16

Well, since some unknown framework has done something to the machine before starting the scheduler, it obviously has done something to that value. Maybe it tried to configure the system clock to some faster value? or maybe just did a wild write and messed up the value.

Also, I would NOT just call vPortSetupTimerInterrupt() a second time to correct the timer period on a clock change. It likely does some other actions that you may not want done, but you just want to change the timer period.

18

Thanks for your replies.

I know that I should not call the vPortSetupTimerInterrupt()function, but I really cannot modify the framework. So I debugged the program step to step to find why the value of SystemCoreClock is incorrect. It turns out that SystemCoreClock was changed in startup_MIMX8QX6_cm4.S.

I started the debug from the entry point, namely the reset handler.

/* Reset Handler */

	.thumb_func
	.align 2
	.globl   Reset_Handler
	.weak    Reset_Handler
	.type    Reset_Handler, %function
Reset_Handler:
	cpsid   i               /* Mask interrupts */
	.equ    VTOR, 0xE000ED08
	ldr     r0, =VTOR
	ldr     r1, =__isr_vector
	str     r1, [r0]
	ldr     r2, [r1]
	msr     msp, r2
#ifndef __NO_SYSTEM_INIT
	ldr   r0,=SystemInit
	blx   r0
#endif
/*     Loop to copy data from read only memory to RAM. The ranges
 *      of copy from/to are specified by following symbols evaluated in
 *      linker script.
 *      __etext: End of code section, i.e., begin of data sections to copy from.
 *      __data_start__/__data_end__: RAM address range that data should be
 *      __noncachedata_start__/__noncachedata_end__ : none cachable region
 *      copied to. Both must be aligned to 4 bytes boundary.  */

	ldr    r1, =__etext
	ldr    r2, =__data_start__
	ldr    r3, =__data_end__
 
#if 1
/* Here are two copies of loop implemenations. First one favors code size
 * and the second one favors performance. Default uses the first one.
 * Change to "#if 0" to use the second one */
.LC0:
    cmp     r2, r3
    ittt    lt
    ldrlt   r0, [r1], #4
    strlt   r0, [r2], #4
    blt    .LC0
#else
    subs    r3, r2
    ble    .LC1
.LC0:
    subs    r3, #4
        ldr    r0, [r1, r3]
        str    r0, [r2, r3]
        bgt    .LC0
    .LC1:
#endif

And the value of SystemCoreClock is modified from 264000000 to 536742401 at:

.LC0:
    cmp     r2, r3
    ittt    lt
    ldrlt   r0, [r1], #4
    strlt   r0, [r2], #4
    blt    .LC0

Does anyone have any idea about this?

A part of the startup_MIMX8QX6_cm4.S is here:

/* ------------------------------------------------------------------------- */
/*  @file:    startup_MIMX8QX6_cm4.s                                         */
/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                       */
/*            MIMX8QX6_cm4                                                   */
/*  @version: 4.0                                                            */
/*  @date:    2018-8-22                                                      */
/*  @build:   b191126                                                        */
/* ------------------------------------------------------------------------- */
/*                                                                           */
/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
/* Copyright 2016-2019 NXP                                                   */
/* All rights reserved.                                                      */
/*                                                                           */
/* SPDX-License-Identifier: BSD-3-Clause                                     */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors                                  */
/*****************************************************************************/
	.syntax unified
	.arch armv7-m

	.section .isr_vector, "a"
	.align 2
	.globl __isr_vector
__isr_vector:
	.long   __StackTop                                      /* Top of Stack */
	.long   Reset_Handler                                   /* Reset Handler */
	.long   NMI_Handler                                     /* NMI Handler*/
	.long   HardFault_Handler                               /* Hard Fault Handler*/
	.long   MemManage_Handler                               /* MPU Fault Handler*/
	.long   BusFault_Handler                                /* Bus Fault Handler*/
	.long   UsageFault_Handler                              /* Usage Fault Handler*/
	.long   0                                               /* Reserved*/
	.long   0                                               /* Reserved*/
	.long   0                                               /* Reserved*/
	.long   0                                               /* Reserved*/
	.long   SVC_Handler                                     /* SVCall Handler*/
	.long   DebugMon_Handler                                /* Debug Monitor Handler*/
	.long   0                                               /* Reserved*/
	.long   PendSV_Handler                                  /* PendSV Handler*/
	.long   SysTick_Handler                                 /* SysTick Handler*/

															/* External Interrupts*/
	.long   Reserved16_IRQHandler                           /* Reserved*/
	.long   Reserved17_IRQHandler                           /* Reserved*/
	.long   Reserved18_IRQHandler                           /* Reserved*/
	.long   Reserved19_IRQHandler                           /* Reserved*/
	.long   Reserved20_IRQHandler                           /* Reserved*/
	.long   M4_MCM_IRQHandler                               /* MCM IRQ*/
	.long   Reserved22_IRQHandler                           /* Reserved*/
	.long   Reserved23_IRQHandler                           /* Reserved*/
	.long   Reserved24_IRQHandler                           /* Reserved*/
	.long   Reserved25_IRQHandler                           /* Reserved*/
	.long   Reserved26_IRQHandler                           /* Reserved*/
	.long   Reserved27_IRQHandler                           /* Reserved*/
	.long   Reserved28_IRQHandler                           /* Reserved*/
	.long   Reserved29_IRQHandler                           /* Reserved*/
	.long   Reserved30_IRQHandler                           /* Reserved*/
	.long   Reserved31_IRQHandler                           /* Reserved*/
	.long   Reserved32_IRQHandler                           /* Reserved*/
	.long   Reserved33_IRQHandler                           /* Reserved*/
	.long   Reserved34_IRQHandler                           /* Reserved*/
	.long   M4_TPM_IRQHandler                               /* Timer PWM Module*/
	.long   Reserved36_IRQHandler                           /* Reserved*/
	.long   Reserved37_IRQHandler                           /* Reserved*/
	.long   M4_LPIT_IRQHandler                              /* Low-Power Periodic Interrupt Timer*/
	.long   Reserved39_IRQHandler                           /* Reserved*/
	.long   Reserved40_IRQHandler                           /* Reserved*/
	.long   M4_LPUART_IRQHandler                            /* Low Power UART*/
	.long   Reserved42_IRQHandler                           /* Reserved*/
	.long   M4_LPI2C_IRQHandler                             /* Low-Power I2C - Logical OR of master and slave interrupts*/
	.long   Reserved44_IRQHandler                           /* Reserved*/
	.long   M4_MU0_B0_IRQHandler                            /* Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts*/
	.long   Reserved46_IRQHandler                           /* Reserved*/
	.long   Reserved47_IRQHandler                           /* Reserved*/
	.long   IRQSTEER_0_IRQHandler                           /* External interrupt 0*/
	.long   IRQSTEER_1_IRQHandler                           /* External interrupt 1*/
	.long   IRQSTEER_2_IRQHandler                           /* External interrupt 2*/
	.long   IRQSTEER_3_IRQHandler                           /* External interrupt 3*/
	.long   IRQSTEER_4_IRQHandler                           /* External interrupt 4*/
	.long   IRQSTEER_5_IRQHandler                           /* External interrupt 5*/
	.long   IRQSTEER_6_IRQHandler                           /* External interrupt 6*/
	.long   IRQSTEER_7_IRQHandler                           /* External interrupt 7*/
	.long   Reserved56_IRQHandler                           /* Reserved*/
	.long   Reserved57_IRQHandler                           /* Reserved*/
	.long   Reserved58_IRQHandler                           /* Reserved*/
	.long   Reserved59_IRQHandler                           /* Reserved*/
	.long   M4_MU0_B1_IRQHandler                            /* Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts*/
	.long   M4_MU0_B2_IRQHandler                            /* Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts*/
	.long   M4_MU0_B3_IRQHandler                            /* Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts*/
	.long   Reserved63_IRQHandler                           /* Reserved*/
	.long   Reserved64_IRQHandler                           /* Reserved*/
	.long   M4_MU1_A_IRQHandler                             /* Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts*/
	.long   M4_SW_IRQHandler                                /* Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low)*/
	.long   Reserved67_IRQHandler                           /* xxx Interrupt 67*/
	.long   Reserved68_IRQHandler                           /* xxx Interrupt 68*/
	.long   Reserved69_IRQHandler                           /* xxx Interrupt 69*/
	.long   Reserved70_IRQHandler                           /* xxx Interrupt 70*/
	.long   Reserved71_IRQHandler                           /* xxx Interrupt 71*/
	.long   Reserved72_IRQHandler                           /* xxx Interrupt 72*/
	.long   Reserved73_IRQHandler                           /* xxx Interrupt 73*/
	.long   Reserved74_IRQHandler                           /* xxx Interrupt 74*/
	.long   Reserved75_IRQHandler                           /* xxx Interrupt 75*/
	.long   Reserved76_IRQHandler                           /* xxx Interrupt 76*/
	.long   Reserved77_IRQHandler                           /* xxx Interrupt 77*/
	.long   Reserved78_IRQHandler                           /* xxx Interrupt 78*/
	.long   Reserved79_IRQHandler                           /* xxx Interrupt 79*/
	.long   Reserved80_IRQHandler                           /* xxx Interrupt 80*/
	.long   Reserved81_IRQHandler                           /* xxx Interrupt 81*/
	.long   Reserved82_IRQHandler                           /* xxx Interrupt 82*/
	.long   Reserved83_IRQHandler                           /* xxx Interrupt 83*/
	.long   Reserved84_IRQHandler                           /* xxx Interrupt 84*/
	.long   Reserved85_IRQHandler                           /* xxx Interrupt 85*/
	.long   Reserved86_IRQHandler                           /* xxx Interrupt 86*/
	.long   Reserved87_IRQHandler                           /* xxx Interrupt 87*/
	.long   Reserved88_IRQHandler                           /* xxx Interrupt 88*/
	.long   Reserved89_IRQHandler                           /* xxx Interrupt 89*/
	.long   Reserved90_IRQHandler                           /* xxx Interrupt 90*/
	.long   Reserved91_IRQHandler                           /* xxx Interrupt 91*/
	.long   Reserved92_IRQHandler                           /* xxx Interrupt 92*/
	.long   Reserved93_IRQHandler                           /* xxx Interrupt 93*/
	.long   Reserved94_IRQHandler                           /* xxx Interrupt 94*/
	.long   Reserved95_IRQHandler                           /* xxx Interrupt 95*/
	.long   Reserved96_IRQHandler                           /* xxx Interrupt 96*/
	.long   Reserved97_IRQHandler                           /* xxx Interrupt 97*/
	.long   Reserved98_IRQHandler                           /* xxx Interrupt 98*/
	.long   A35_NEXTERRIRQ_IRQHandler                       /* Shared Int Source nEXTERRIRQ from A35 Sub-System*/
	.long   A35_NINTERRIRQ_IRQHandler                       /* Shared Int Source nINTERRIRQ from A35 Sub-System*/
	.long   Reserved101_IRQHandler                          /* xxx Interrupt 101*/
	.long   Reserved102_IRQHandler                          /* xxx Interrupt 102*/
	.long   Reserved103_IRQHandler                          /* xxx Interrupt 103*/
	.long   Reserved104_IRQHandler                          /* xxx Interrupt 104*/
	.long   Reserved105_IRQHandler                          /* xxx Interrupt 105*/
	.long   Reserved106_IRQHandler                          /* xxx Interrupt 106*/
	.long   Reserved107_IRQHandler                          /* xxx Interrupt 107*/
	.long   Reserved108_IRQHandler                          /* xxx Interrupt 108*/
	.long   Reserved109_IRQHandler                          /* xxx Interrupt 109*/
	.long   Reserved110_IRQHandler                          /* xxx Interrupt 110*/
	.long   Reserved111_IRQHandler                          /* xxx Interrupt 111*/
	.long   Reserved112_IRQHandler                          /* xxx Interrupt 112*/
	.long   Reserved113_IRQHandler                          /* xxx Interrupt 113*/
	.long   Reserved114_IRQHandler                          /* xxx Interrupt 114*/
	.long   M4_INT_OUT0_IRQHandler                          /* Shared Int Source INT_OUT[0] from M4 Sub-System*/
	.long   M4_INT_OUT1_IRQHandler                          /* Shared Int Source INT_OUT[1] from M4 Sub-System*/
	.long   M4_INT_OUT2_IRQHandler                          /* Shared Int Source INT_OUT[2] from M4 Sub-System*/
	.long   M4_INT_OUT3_IRQHandler                          /* Shared Int Source INT_OUT[3] from M4 Sub-System*/
	.long   M4_INT_OUT4_IRQHandler                          /* Shared Int Source INT_OUT[4] from M4 Sub-System*/
	.long   M4_INT_OUT5_IRQHandler                          /* Shared Int Source INT_OUT[5] from M4 Sub-System*/
	.long   M4_INT_OUT6_IRQHandler                          /* Shared Int Source INT_OUT[6] from M4 Sub-System*/
	.long   M4_INT_OUT7_IRQHandler                          /* Shared Int Source INT_OUT[7] from M4 Sub-System*/
	.long   Reserved123_IRQHandler                          /* xxx Interrupt 123*/
	.long   Reserved124_IRQHandler                          /* xxx Interrupt 124*/
	.long   Reserved125_IRQHandler                          /* xxx Interrupt 125*/
	.long   Reserved126_IRQHandler                          /* xxx Interrupt 126*/
	.long   Reserved127_IRQHandler                          /* xxx Interrupt 127*/
	.long   Reserved128_IRQHandler                          /* xxx Interrupt 128*/
	.long   Reserved129_IRQHandler                          /* xxx Interrupt 129*/
	.long   Reserved130_IRQHandler                          /* xxx Interrupt 130*/
	.long   Reserved131_IRQHandler                          /* xxx Interrupt 131*/
	.long   Reserved132_IRQHandler                          /* xxx Interrupt 132*/
	.long   Reserved133_IRQHandler                          /* xxx Interrupt 133*/
	.long   Reserved134_IRQHandler                          /* xxx Interrupt 134*/
	.long   Reserved135_IRQHandler                          /* xxx Interrupt 135*/
	.long   Reserved136_IRQHandler                          /* xxx Interrupt 136*/
	.long   Reserved137_IRQHandler                          /* xxx Interrupt 137*/
	.long   Reserved138_IRQHandler                          /* xxx Interrupt 138*/
	.long   DISPLAY0_INT_OUT0_IRQHandler                    /* Shared Int Source INT_OUT[0] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT1_IRQHandler                    /* Shared Int Source INT_OUT[1] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT2_IRQHandler                    /* Shared Int Source INT_OUT[2] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT3_IRQHandler                    /* Shared Int Source INT_OUT[3] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT4_IRQHandler                    /* Shared Int Source INT_OUT[4] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT5_IRQHandler                    /* Shared Int Source INT_OUT[5] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT6_IRQHandler                    /* Shared Int Source INT_OUT[6] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT7_IRQHandler                    /* Shared Int Source INT_OUT[7] from Display0 Sub-System*/
	.long   DISPLAY0_RESERVED_IRQHandler                    /* Shared Int Source Reserved from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT9_IRQHandler                    /* Shared Int Source INT_OUT[9] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT10_IRQHandler                   /* Shared Int Source INT_OUT[10] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT11_IRQHandler                   /* Shared Int Source INT_OUT[11] from Display0 Sub-System*/
	.long   DISPLAY0_INT_OUT12_IRQHandler                   /* Shared Int Source INT_OUT[12] from Display0 Sub-System*/
	.long   Reserved152_IRQHandler                          /* xxx Interrupt 152*/
	.long   Reserved153_IRQHandler                          /* xxx Interrupt 153*/
	.long   Reserved154_IRQHandler                          /* xxx Interrupt 154*/
	.long   Reserved155_IRQHandler                          /* xxx Interrupt 155*/
	.long   Reserved156_IRQHandler                          /* xxx Interrupt 156*/
	.long   Reserved157_IRQHandler                          /* xxx Interrupt 157*/
	.long   MIPI_DSI0_INT_OUT_IRQHandler                    /* Shared Int Source INT_OUT from MIPI_DSI0 Sub-System*/
	.long   MIPI_DSI1_INT_OUT_IRQHandler                    /* Shared Int Source INT_OUT from MIPI_DSI1 Sub-System*/
	.long   Reserved160_IRQHandler                          /* xxx Interrupt 160*/
	.long   LCD_MOD_INT_IRQHandler                          /* Shared Int Source INT_OUT from ADMA Sub-System*/
	.long   LCD_PWM_INT_IRQHandler                          /* Shared Int Source INT_OUT from ADMA Sub-System*/
	.long   GPU0_XAQ2_INTR_IRQHandler                       /* Shared Int Source xaq2_intr from GPU0 Sub-System*/
	.long   Reserved164_IRQHandler                          /* xxx Interrupt 164*/
	.long   ADMA_EDMA2_INT_IRQHandler                       /* Shared Int Source eDMA2_INT from ADMA Sub-System*/
	.long   ADMA_EDMA2_ERR_INT_IRQHandler                   /* Shared Int Source eDMA2_ERR_INT from ADMA Sub-System*/
	.long   ADMA_EDMA3_INT_IRQHandler                       /* Shared Int Source eDMA3_INT from ADMA Sub-System*/
	.long   ADMA_EDMA3_ERR_INT_IRQHandler                   /* Shared Int Source eDMA3_ERR_INT from ADMA Sub-System*/
	.long   Reserved169_IRQHandler                          /* xxx Interrupt 169*/
	.long   Reserved170_IRQHandler                          /* xxx Interrupt 170*/
	.long   Reserved171_IRQHandler                          /* xxx Interrupt 171*/
	.long   Reserved172_IRQHandler                          /* xxx Interrupt 172*/
	.long   Reserved173_IRQHandler                          /* xxx Interrupt 173*/
	.long   Reserved174_IRQHandler                          /* xxx Interrupt 174*/
	.long   Reserved175_IRQHandler                          /* xxx Interrupt 175*/
	.long   Reserved176_IRQHandler                          /* xxx Interrupt 176*/
	.long   Reserved177_IRQHandler                          /* xxx Interrupt 177*/
	.long   Reserved178_IRQHandler                          /* xxx Interrupt 178*/
	.long   LSIO_GPT0_INT_IRQHandler                        /* Shared Int Source GPT0_INT from LSIO Sub-System*/
	.long   LSIO_GPT1_INT_IRQHandler                        /* Shared Int Source GPT1_INT from LSIO Sub-System*/
	.long   LSIO_GPT2_INT_IRQHandler                        /* Shared Int Source GPT2_INT from LSIO Sub-System*/
	.long   LSIO_GPT3_INT_IRQHandler                        /* Shared Int Source GPT3_INT from LSIO Sub-System*/
	.long   LSIO_GPT4_INT_IRQHandler                        /* Shared Int Source GPT4_INT from LSIO Sub-System*/
	.long   LSIO_KPP_INT_IRQHandler                         /* Shared Int Source KPP_INT from LSIO Sub-System*/
	.long   Reserved185_IRQHandler                          /* xxx Interrupt 185*/
	.long   Reserved186_IRQHandler                          /* xxx Interrupt 186*/
	.long   Reserved187_IRQHandler                          /* xxx Interrupt 187*/
	.long   Reserved188_IRQHandler                          /* xxx Interrupt 188*/
	.long   Reserved189_IRQHandler                          /* xxx Interrupt 189*/
	.long   Reserved190_IRQHandler                          /* xxx Interrupt 190*/
	.long   LSIO_OCTASPI0_INT_IRQHandler                    /* Shared Int Source OctaSPI0_INT from LSIO Sub-System*/
	.long   LSIO_OCTASPI1_INT_IRQHandler                    /* Shared Int Source OctaSPI1_INT from LSIO Sub-System*/
	.long   LSIO_PWM0_INT_IRQHandler                        /* Shared Int Source PWM0_INT from LSIO Sub-System*/
	.long   LSIO_PWM1_INT_IRQHandler                        /* Shared Int Source PWM1_INT from LSIO Sub-System*/
	.long   LSIO_PWM2_INT_IRQHandler                        /* Shared Int Source PWM2_INT from LSIO Sub-System*/
	.long   LSIO_PWM3_INT_IRQHandler                        /* Shared Int Source PWM3_INT from LSIO Sub-System*/
	.long   LSIO_PWM4_INT_IRQHandler                        /* Shared Int Source PWM4_INT from LSIO Sub-System*/
	.long   LSIO_PWM5_INT_IRQHandler                        /* Shared Int Source PWM5_INT from LSIO Sub-System*/
	.long   LSIO_PWM6_INT_IRQHandler                        /* Shared Int Source PWM6_INT from LSIO Sub-System*/
	.long   LSIO_PWM7_INT_IRQHandler                        /* Shared Int Source PWM7_INT from LSIO Sub-System*/
	.long   HSIO_PCIEB_MSI_CTRL_INT_IRQHandler              /* Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System*/
	.long   HSIO_PCIEB_CLK_REQ_INT_IRQHandler               /* Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System*/
	.long   HSIO_PCIEB_DMA_INT_IRQHandler                   /* Shared Int Source PCIeB_DMA_INT from HSIO Sub-System*/
	.long   HSIO_PCIEB_INT_D_IRQHandler                     /* Shared Int Source PCIeB_INT_D from HSIO Sub-System*/
	.long   HSIO_PCIEB_INT_C_IRQHandler                     /* Shared Int Source PCIeB_INT_C from HSIO Sub-System*/
	.long   HSIO_PCIEB_INT_B_IRQHandler                     /* Shared Int Source PCIeB_INT_B from HSIO Sub-System*/
	.long   HSIO_PCIEB_INT_A_IRQHandler                     /* Shared Int Source PCIeB_INT_A from HSIO Sub-System*/
	.long   HSIO_PCIEB_SMLH_REQ_RST_IRQHandler              /* Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System*/
	.long   HSIO_PCIEB_GPIO_WAKEUP0_IRQHandler              /* Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System*/
	.long   HSIO_PCIEB_GPIO_WAKEUP1_IRQHandler              /* Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System*/
	.long   SCU_INT_OUT0_IRQHandler                         /* Shared Int Source INT_OUT[0] from SCU Sub-System*/
	.long   SCU_INT_OUT1_IRQHandler                         /* Shared Int Source INT_OUT[1] from SCU Sub-System*/
	.long   SCU_INT_OUT2_IRQHandler                         /* Shared Int Source INT_OUT[2] from SCU Sub-System*/
	.long   SCU_INT_OUT3_IRQHandler                         /* Shared Int Source INT_OUT[3] from SCU Sub-System*/
	.long   SCU_INT_OUT4_IRQHandler                         /* Shared Int Source INT_OUT[4] from SCU Sub-System*/
	.long   SCU_INT_OUT5_IRQHandler                         /* Shared Int Source INT_OUT[5] from SCU Sub-System*/
	.long   SCU_INT_OUT6_IRQHandler                         /* Shared Int Source INT_OUT[6] from SCU Sub-System*/
	.long   SCU_INT_OUT7_IRQHandler                         /* Shared Int Source INT_OUT[7] from SCU Sub-System*/
	.long   SCU_SYS_COUNT_INT0_IRQHandler                   /* Shared Int Source SYS_COUNT_INT0 from SCU Sub-System*/
	.long   SCU_SYS_COUNT_INT1_IRQHandler                   /* Shared Int Source SYS_COUNT_INT1 from SCU Sub-System*/
	.long   SCU_SYS_COUNT_INT2_IRQHandler                   /* Shared Int Source SYS_COUNT_INT2 from SCU Sub-System*/
	.long   SCU_SYS_COUNT_INT3_IRQHandler                   /* Shared Int Source SYS_COUNT_INT3 from SCU Sub-System*/
	.long   Reserved223_IRQHandler                          /* xxx Interrupt 223*/
	.long   Reserved224_IRQHandler                          /* xxx Interrupt 224*/
	.long   Reserved225_IRQHandler                          /* xxx Interrupt 225*/
	.long   Reserved226_IRQHandler                          /* xxx Interrupt 226*/
	.long   DRC_ECC_CORRECT_INT_IRQHandler                  /* Shared Int Source ECC_CORRECT_INT from DRC Sub-System*/
	.long   DRC_ECC_NCORRECT_INT_IRQHandler                 /* Shared Int Source ECC_NCORRECT_INT from DRC Sub-System*/
	.long   DRC_SBR_DONE_INT_IRQHandler                     /* Shared Int Source SBR_DONE_INT from DRC Sub-System*/
	.long   DRC_PERF_CNT_INT_IRQHandler                     /* Shared Int Source PERF_CNT_INT from DRC Sub-System*/
	.long   Reserved231_IRQHandler                          /* xxx Interrupt 231*/
	.long   Reserved232_IRQHandler                          /* xxx Interrupt 232*/
	.long   Reserved233_IRQHandler                          /* xxx Interrupt 233*/
	.long   Reserved234_IRQHandler                          /* xxx Interrupt 234*/
	.long   LSIO_GPIO_INT0_IRQHandler                       /* Shared Int Source GPIO_INT[0] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT1_IRQHandler                       /* Shared Int Source GPIO_INT[1] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT2_IRQHandler                       /* Shared Int Source GPIO_INT[2] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT3_IRQHandler                       /* Shared Int Source GPIO_INT[3] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT4_IRQHandler                       /* Shared Int Source GPIO_INT[4] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT5_IRQHandler                       /* Shared Int Source GPIO_INT[5] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT6_IRQHandler                       /* Shared Int Source GPIO_INT[6] from LSIO Sub-System*/
	.long   LSIO_GPIO_INT7_IRQHandler                       /* Shared Int Source GPIO_INT[7] from LSIO Sub-System*/
	.long   Reserved243_IRQHandler                          /* xxx Interrupt 243*/
	.long   Reserved244_IRQHandler                          /* xxx Interrupt 244*/
	.long   Reserved245_IRQHandler                          /* xxx Interrupt 245*/
	.long   Reserved246_IRQHandler                          /* xxx Interrupt 246*/
	.long   Reserved247_IRQHandler                          /* xxx Interrupt 247*/
	.long   Reserved248_IRQHandler                          /* xxx Interrupt 248*/
	.long   Reserved249_IRQHandler                          /* xxx Interrupt 249*/
	.long   Reserved250_IRQHandler                          /* xxx Interrupt 250*/
	.long   Reserved251_IRQHandler                          /* xxx Interrupt 251*/
	.long   Reserved252_IRQHandler                          /* xxx Interrupt 252*/
	.long   Reserved253_IRQHandler                          /* xxx Interrupt 253*/
	.long   Reserved254_IRQHandler                          /* xxx Interrupt 254*/
	.long   Reserved255_IRQHandler                          /* xxx Interrupt 255*/
	.long   Reserved256_IRQHandler                          /* xxx Interrupt 256*/
	.long   Reserved257_IRQHandler                          /* xxx Interrupt 257*/
	.long   Reserved258_IRQHandler                          /* xxx Interrupt 258*/
	.long   Reserved259_IRQHandler                          /* xxx Interrupt 259*/
	.long   Reserved260_IRQHandler                          /* xxx Interrupt 260*/
	.long   Reserved261_IRQHandler                          /* xxx Interrupt 261*/
	.long   Reserved262_IRQHandler                          /* xxx Interrupt 262*/
	.long   Reserved263_IRQHandler                          /* xxx Interrupt 263*/
	.long   Reserved264_IRQHandler                          /* xxx Interrupt 264*/
	.long   Reserved265_IRQHandler                          /* xxx Interrupt 265*/
	.long   Reserved266_IRQHandler                          /* xxx Interrupt 266*/
	.long   Reserved267_IRQHandler                          /* xxx Interrupt 267*/
	.long   Reserved268_IRQHandler                          /* xxx Interrupt 268*/
	.long   Reserved269_IRQHandler                          /* xxx Interrupt 269*/
	.long   Reserved270_IRQHandler                          /* xxx Interrupt 270*/
	.long   Reserved271_IRQHandler                          /* xxx Interrupt 271*/
	.long   Reserved272_IRQHandler                          /* xxx Interrupt 272*/
	.long   Reserved273_IRQHandler                          /* xxx Interrupt 273*/
	.long   Reserved274_IRQHandler                          /* xxx Interrupt 274*/
	.long   LSIO_MU0_INT_IRQHandler                         /* Shared Int Source MU0_INT from LSIO Sub-System*/
	.long   LSIO_MU1_INT_IRQHandler                         /* Shared Int Source MU1_INT from LSIO Sub-System*/
	.long   LSIO_MU2_INT_IRQHandler                         /* Shared Int Source MU2_INT from LSIO Sub-System*/
	.long   LSIO_MU3_INT_IRQHandler                         /* Shared Int Source MU3_INT from LSIO Sub-System*/
	.long   LSIO_MU4_INT_IRQHandler                         /* Shared Int Source MU4_INT from LSIO Sub-System*/
	.long   Reserved280_IRQHandler                          /* xxx Interrupt 280*/
	.long   Reserved281_IRQHandler                          /* xxx Interrupt 281*/
	.long   Reserved282_IRQHandler                          /* xxx Interrupt 282*/
	.long   LSIO_MU5_INT_A_IRQHandler                       /* Shared Int Source MU5_INT_A from LSIO Sub-System*/
	.long   LSIO_MU6_INT_A_IRQHandler                       /* Shared Int Source MU6_INT_A from LSIO Sub-System*/
	.long   LSIO_MU7_INT_A_IRQHandler                       /* Shared Int Source MU7_INT_A from LSIO Sub-System*/
	.long   LSIO_MU8_INT_A_IRQHandler                       /* Shared Int Source MU8_INT_A from LSIO Sub-System*/
	.long   LSIO_MU9_INT_A_IRQHandler                       /* Shared Int Source MU9_INT_A from LSIO Sub-System*/
	.long   LSIO_MU10_INT_A_IRQHandler                      /* Shared Int Source MU10_INT_A from LSIO Sub-System*/
	.long   LSIO_MU11_INT_A_IRQHandler                      /* Shared Int Source MU11_INT_A from LSIO Sub-System*/
	.long   LSIO_MU12_INT_A_IRQHandler                      /* Shared Int Source MU12_INT_A from LSIO Sub-System*/
	.long   LSIO_MU13_INT_A_IRQHandler                      /* Shared Int Source MU13_INT_A from LSIO Sub-System*/
	.long   Reserved292_IRQHandler                          /* xxx Interrupt 292*/
	.long   Reserved293_IRQHandler                          /* xxx Interrupt 293*/
	.long   Reserved294_IRQHandler                          /* xxx Interrupt 294*/
	.long   Reserved295_IRQHandler                          /* xxx Interrupt 295*/
	.long   Reserved296_IRQHandler                          /* xxx Interrupt 296*/
	.long   Reserved297_IRQHandler                          /* xxx Interrupt 297*/
	.long   Reserved298_IRQHandler                          /* xxx Interrupt 298*/
	.long   LSIO_MU5_INT_B_IRQHandler                       /* Shared Int Source MU5_INT_B from LSIO Sub-System*/
	.long   LSIO_MU6_INT_B_IRQHandler                       /* Shared Int Source MU6_INT_B from LSIO Sub-System*/
	.long   LSIO_MU7_INT_B_IRQHandler                       /* Shared Int Source MU7_INT_B from LSIO Sub-System*/
	.long   LSIO_MU8_INT_B_IRQHandler                       /* Shared Int Source MU8_INT_B from LSIO Sub-System*/
	.long   LSIO_MU9_INT_B_IRQHandler                       /* Shared Int Source MU9_INT_B from LSIO Sub-System*/
	.long   LSIO_MU10_INT_B_IRQHandler                      /* Shared Int Source MU10_INT_B from LSIO Sub-System*/
	.long   LSIO_MU11_INT_B_IRQHandler                      /* Shared Int Source MU11_INT_B from LSIO Sub-System*/
	.long   LSIO_MU12_INT_B_IRQHandler                      /* Shared Int Source MU12_INT_B from LSIO Sub-System*/
	.long   LSIO_MU13_INT_B_IRQHandler                      /* Shared Int Source MU13_INT_B from LSIO Sub-System*/
	.long   Reserved308_IRQHandler                          /* xxx Interrupt 308*/
	.long   Reserved309_IRQHandler                          /* xxx Interrupt 309*/
	.long   Reserved310_IRQHandler                          /* xxx Interrupt 310*/
	.long   Reserved311_IRQHandler                          /* xxx Interrupt 311*/
	.long   Reserved312_IRQHandler                          /* xxx Interrupt 312*/
	.long   Reserved313_IRQHandler                          /* xxx Interrupt 313*/
	.long   Reserved314_IRQHandler                          /* xxx Interrupt 314*/
	.long   ADMA_SPI0_INT_IRQHandler                        /* Shared Int Source SPI0_INT from ADMA Sub-System*/
	.long   ADMA_SPI1_INT_IRQHandler                        /* Shared Int Source SPI1_INT from ADMA Sub-System*/
	.long   ADMA_SPI2_INT_IRQHandler                        /* Shared Int Source SPI2_INT from ADMA Sub-System*/
	.long   ADMA_SPI3_INT_IRQHandler                        /* Shared Int Source SPI3_INT from ADMA Sub-System*/
	.long   ADMA_I2C0_INT_IRQHandler                        /* Shared Int Source I2C0_INT from ADMA Sub-System*/
	.long   ADMA_I2C1_INT_IRQHandler                        /* Shared Int Source I2C1_INT from ADMA Sub-System*/
	.long   ADMA_I2C2_INT_IRQHandler                        /* Shared Int Source I2C2_INT from ADMA Sub-System*/
	.long   ADMA_I2C3_INT_IRQHandler                        /* Shared Int Source I2C3_INT from ADMA Sub-System*/
	.long   ADMA_I2C4_INT_IRQHandler                        /* Shared Int Source I2C4_INT from ADMA Sub-System*/
	.long   ADMA_UART0_INT_IRQHandler                       /* Shared Int Source UART0_INT from ADMA Sub-System*/
	.long   ADMA_UART1_INT_IRQHandler                       /* Shared Int Source UART1_INT from ADMA Sub-System*/
	.long   ADMA_UART2_INT_IRQHandler                       /* Shared Int Source UART2_INT from ADMA Sub-System*/
	.long   ADMA_UART3_INT_IRQHandler                       /* Shared Int Source UART3_INT from ADMA Sub-System*/
	.long   Reserved328_IRQHandler                          /* xxx Interrupt 328*/
	.long   Reserved329_IRQHandler                          /* xxx Interrupt 329*/
	.long   Reserved330_IRQHandler                          /* xxx Interrupt 330*/
	.long   CONNECTIVITY_USDHC0_INT_IRQHandler              /* Shared Int Source uSDHC0_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_USDHC1_INT_IRQHandler              /* Shared Int Source uSDHC1_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_USDHC2_INT_IRQHandler              /* Shared Int Source uSDHC2_INT from Connectivity Sub-System*/
	.long   ADMA_FLEXCAN0_INT_IRQHandler                    /* Shared Int Source FlexCAN0_INT from ADMA Sub-System*/
	.long   ADMA_FLEXCAN1_INT_IRQHandler                    /* Shared Int Source FlexCAN1_INT from ADMA Sub-System*/
	.long   ADMA_FLEXCAN2_INT_IRQHandler                    /* Shared Int Source FlexCAN2_INT from ADMA Sub-System*/
	.long   ADMA_FTM0_INT_IRQHandler                        /* Shared Int Source FTM0_INT from ADMA Sub-System*/
	.long   ADMA_FTM1_INT_IRQHandler                        /* Shared Int Source FTM1_INT from ADMA Sub-System*/
	.long   ADMA_ADC0_INT_IRQHandler                        /* Shared Int Source ADC0_INT from ADMA Sub-System*/
	.long   Reserved340_IRQHandler                          /* xxx Interrupt 340*/
	.long   ADMA_EXTERNAL_DMA_INT_0_IRQHandler              /* Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System*/
	.long   ADMA_EXTERNAL_DMA_INT_1_IRQHandler              /* Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System*/
	.long   ADMA_EXTERNAL_DMA_INT_2_IRQHandler              /* Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System*/
	.long   ADMA_EXTERNAL_DMA_INT_3_IRQHandler              /* Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System*/
	.long   ADMA_EXTERNAL_DMA_INT_4_IRQHandler              /* Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System*/
	.long   ADMA_EXTERNAL_DMA_INT_5_IRQHandler              /* Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System*/
	.long   Reserved347_IRQHandler                          /* xxx Interrupt 347*/
	.long   Reserved348_IRQHandler                          /* xxx Interrupt 348*/
	.long   Reserved349_IRQHandler                          /* xxx Interrupt 349*/
	.long   Reserved350_IRQHandler                          /* xxx Interrupt 350*/
	.long   Reserved351_IRQHandler                          /* xxx Interrupt 351*/
	.long   Reserved352_IRQHandler                          /* xxx Interrupt 352*/
	.long   Reserved353_IRQHandler                          /* xxx Interrupt 353*/
	.long   Reserved354_IRQHandler                          /* xxx Interrupt 354*/
	.long   CONNECTIVITY_ENET0_FRAME1_INT_IRQHandler        /* Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET0_FRAME2_INT_IRQHandler        /* Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQHandler  /* Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET0_TIMER_INT_IRQHandler         /* Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET1_FRAME1_INT_IRQHandler        /* Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET1_FRAME2_INT_IRQHandler        /* Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQHandler  /* Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ENET1_TIMER_INT_IRQHandler         /* Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_DTCP_INT_IRQHandler                /* Shared Int Source DTCP_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_MLB_INT_IRQHandler                 /* Shared Int Source MLB_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_MLB_AHB_INT_IRQHandler             /* Shared Int Source MLB_AHB_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_USB_OTG_INT_IRQHandler             /* Shared Int Source USB_OTG_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_USB_HOST_INT_IRQHandler            /* Shared Int Source USB_HOST_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_UTMI_INT_IRQHandler                /* Shared Int Source UTMI_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_WAKEUP_INT_IRQHandler              /* Shared Int Source WAKEUP_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_USB3_INT_IRQHandler                /* Shared Int Source USB3_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ND_FLASH_BCH_INT_IRQHandler        /* Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_ND_FLASH_GPMI_INT_IRQHandler       /* Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_APBHDMA_IRQHandler                 /* Shared Int Source APBHDMA from Connectivity Sub-System*/
	.long   CONNECTIVITY_DMA_INT_IRQHandler                 /* Shared Int Source DMA_INT from Connectivity Sub-System*/
	.long   CONNECTIVITY_DMA_ERR_INT_IRQHandler             /* Shared Int Source DMA_ERR_INT from Connectivity Sub-System*/
	.long   Reserved376_IRQHandler                          /* xxx Interrupt 376*/
	.long   Reserved377_IRQHandler                          /* xxx Interrupt 377*/
	.long   Reserved378_IRQHandler                          /* xxx Interrupt 378*/
	.long   Reserved379_IRQHandler                          /* xxx Interrupt 379*/
	.long   Reserved380_IRQHandler                          /* xxx Interrupt 380*/
	.long   Reserved381_IRQHandler                          /* xxx Interrupt 381*/
	.long   Reserved382_IRQHandler                          /* xxx Interrupt 382*/
	.long   Reserved383_IRQHandler                          /* xxx Interrupt 383*/
	.long   Reserved384_IRQHandler                          /* xxx Interrupt 384*/
	.long   Reserved385_IRQHandler                          /* xxx Interrupt 385*/
	.long   Reserved386_IRQHandler                          /* xxx Interrupt 386*/
	.long   IMAGING_MSI_INT_IRQHandler                      /* Shared Int Source MSI_INT from Imaging Sub-System*/
	.long   Reserved388_IRQHandler                          /* xxx Interrupt 388*/
	.long   Reserved389_IRQHandler                          /* xxx Interrupt 389*/
	.long   Reserved390_IRQHandler                          /* xxx Interrupt 390*/
	.long   Reserved391_IRQHandler                          /* xxx Interrupt 391*/
	.long   Reserved392_IRQHandler                          /* xxx Interrupt 392*/
	.long   Reserved393_IRQHandler                          /* xxx Interrupt 393*/
	.long   Reserved394_IRQHandler                          /* xxx Interrupt 394*/
	.long   Reserved395_IRQHandler                          /* xxx Interrupt 395*/
	.long   IMAGING_PDMA_STREAM0_INT_IRQHandler             /* Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM1_INT_IRQHandler             /* Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM2_INT_IRQHandler             /* Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM3_INT_IRQHandler             /* Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM4_INT_IRQHandler             /* Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM5_INT_IRQHandler             /* Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM6_INT_IRQHandler             /* Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System*/
	.long   IMAGING_PDMA_STREAM7_INT_IRQHandler             /* Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_ENC0_INT_IRQHandler               /* Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_ENC1_INT_IRQHandler               /* Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_ENC2_INT_IRQHandler               /* Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_ENC3_INT_IRQHandler               /* Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_DEC0_INT_IRQHandler               /* Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_DEC1_INT_IRQHandler               /* Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_DEC2_INT_IRQHandler               /* Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System*/
	.long   IMAGING_MJPEG_DEC3_INT_IRQHandler               /* Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System*/
	.long   Reserved412_IRQHandler                          /* xxx Interrupt 412*/
	.long   ADMA_SAI0_MOD_INT_IRQHandler                    /* Shared Int Source SAI0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SAI0_DMA_INT_IRQHandler                    /* Shared Int Source SAI0_DMA_INT from ADMA Sub-System*/
	.long   ADMA_SAI1_MOD_INT_IRQHandler                    /* Shared Int Source SAI1_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SAI1_DMA_INT_IRQHandler                    /* Shared Int Source SAI1_DMA_INT from ADMA Sub-System*/
	.long   ADMA_SAI2_MOD_INT_IRQHandler                    /* Shared Int Source SAI2_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SAI2_DMA_INT_IRQHandler                    /* Shared Int Source SAI2_DMA_INT from ADMA Sub-System*/
	.long   MIPI_CSI0_OUT_INT_IRQHandler                    /* Shared Int Source OUT_INT from MIPI_CSI0 Sub-System*/
	.long   Reserved420_IRQHandler                          /* xxx Interrupt 420*/
	.long   Reserved421_IRQHandler                          /* xxx Interrupt 421*/
	.long   ADMA_SAI3_MOD_INT_IRQHandler                    /* Shared Int Source SAI3_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SAI3_DMA_INT_IRQHandler                    /* Shared Int Source SAI3_DMA_INT from ADMA Sub-System*/
	.long   Reserved424_IRQHandler                          /* xxx Interrupt 424*/
	.long   Reserved425_IRQHandler                          /* xxx Interrupt 425*/
	.long   Reserved426_IRQHandler                          /* xxx Interrupt 426*/
	.long   Reserved427_IRQHandler                          /* xxx Interrupt 427*/
	.long   ADMA_SAI4_MOD_INT_IRQHandler                    /* Shared Int Source SAI4_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SAI4_DMA_INT_IRQHandler                    /* Shared Int Source SAI4_DMA_INT from ADMA Sub-System*/
	.long   ADMA_SAI5_MOD_INT_IRQHandler                    /* Shared Int Source SAI5_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SAI5_DMA_INT_IRQHandler                    /* Shared Int Source SAI5_DMA_INT from ADMA Sub-System*/
	.long   Reserved432_IRQHandler                          /* xxx Interrupt 432*/
	.long   Reserved433_IRQHandler                          /* xxx Interrupt 433*/
	.long   Reserved434_IRQHandler                          /* xxx Interrupt 434*/
	.long   ADMA_SPI0_MOD_INT_IRQHandler                    /* Shared Int Source SPI0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SPI1_MOD_INT_IRQHandler                    /* Shared Int Source SPI1_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SPI2_MOD_INT_IRQHandler                    /* Shared Int Source SPI2_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SPI3_MOD_INT_IRQHandler                    /* Shared Int Source SPI3_MOD_INT from ADMA Sub-System*/
	.long   ADMA_I2C0_MOD_INT_IRQHandler                    /* Shared Int Source I2C0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_I2C1_MOD_INT_IRQHandler                    /* Shared Int Source I2C1_MOD_INT from ADMA Sub-System*/
	.long   ADMA_I2C2_MOD_INT_IRQHandler                    /* Shared Int Source I2C2_MOD_INT from ADMA Sub-System*/
	.long   ADMA_I2C3_MOD_INT_IRQHandler                    /* Shared Int Source I2C3_MOD_INT from ADMA Sub-System*/
	.long   Reserved443_IRQHandler                          /* xxx Interrupt 443*/
	.long   ADMA_UART0_MOD_INT_IRQHandler                   /* Shared Int Source UART0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_UART1_MOD_INT_IRQHandler                   /* Shared Int Source UART1_MOD_INT from ADMA Sub-System*/
	.long   ADMA_UART2_MOD_INT_IRQHandler                   /* Shared Int Source UART2_MOD_INT from ADMA Sub-System*/
	.long   ADMA_UART3_MOD_INT_IRQHandler                   /* Shared Int Source UART3_MOD_INT from ADMA Sub-System*/
	.long   Reserved448_IRQHandler                          /* xxx Interrupt 448*/
	.long   Reserved449_IRQHandler                          /* xxx Interrupt 449*/
	.long   Reserved450_IRQHandler                          /* xxx Interrupt 450*/
	.long   ADMA_FLEXCAN0_MOD_INT_IRQHandler                /* Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_FLEXCAN1_MOD_INT_IRQHandler                /* Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System*/
	.long   ADMA_FLEXCAN2_MOD_INT_IRQHandler                /* Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System*/
	.long   ADMA_FTM0_MOD_INT_IRQHandler                    /* Shared Int Source FTM0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_FTM1_MOD_INT_IRQHandler                    /* Shared Int Source FTM1_MOD_INT from ADMA Sub-System*/
	.long   ADMA_ADC0_MOD_INT_IRQHandler                    /* Shared Int Source ADC0_MOD_INT from ADMA Sub-System*/
	.long   Reserved457_IRQHandler                          /* xxx Interrupt 457*/
	.long   ADMA_FLEXCAN0_DMA_INT_IRQHandler                /* Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System*/
	.long   ADMA_FLEXCAN1_DMA_INT_IRQHandler                /* Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System*/
	.long   ADMA_FLEXCAN2_DMA_INT_IRQHandler                /* Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System*/
	.long   ADMA_FTM0_DMA_INT_IRQHandler                    /* Shared Int Source FTM0_DMA_INT from ADMA Sub-System*/
	.long   ADMA_FTM1_DMA_INT_IRQHandler                    /* Shared Int Source FTM1_DMA_INT from ADMA Sub-System*/
	.long   ADMA_ADC0_DMA_INT_IRQHandler                    /* Shared Int Source ADC0_DMA_INT from ADMA Sub-System*/
	.long   ADMA_ADC1_DMA_INT_IRQHandler                    /* Shared Int Source ADC1_DMA_INT from ADMA Sub-System*/
	.long   Reserved465_IRQHandler                          /* xxx Interrupt 465*/
	.long   Reserved466_IRQHandler                          /* xxx Interrupt 466*/
	.long   ADMA_EDMA0_INT_IRQHandler                       /* Shared Int Source eDMA0_INT from ADMA Sub-System*/
	.long   ADMA_EDMA0_ERR_INT_IRQHandler                   /* Shared Int Source eDMA0_ERR_INT from ADMA Sub-System*/
	.long   ADMA_EDMA1_INT_IRQHandler                       /* Shared Int Source eDMA1_INT from ADMA Sub-System*/
	.long   ADMA_EDMA1_ERR_INT_IRQHandler                   /* Shared Int Source eDMA1_ERR_INT from ADMA Sub-System*/
	.long   ADMA_ASRC0_INT1_IRQHandler                      /* Shared Int Source ASRC0_INT1 from ADMA Sub-System*/
	.long   ADMA_ASRC0_INT2_IRQHandler                      /* Shared Int Source ASRC0_INT2 from ADMA Sub-System*/
	.long   ADMA_DMA0_CH0_INT_IRQHandler                    /* Shared Int Source DMA0_CH0_INT from ADMA Sub-System*/
	.long   ADMA_DMA0_CH1_INT_IRQHandler                    /* Shared Int Source DMA0_CH1_INT from ADMA Sub-System*/
	.long   ADMA_DMA0_CH2_INT_IRQHandler                    /* Shared Int Source DMA0_CH2_INT from ADMA Sub-System*/
	.long   ADMA_DMA0_CH3_INT_IRQHandler                    /* Shared Int Source DMA0_CH3_INT from ADMA Sub-System*/
	.long   ADMA_DMA0_CH4_INT_IRQHandler                    /* Shared Int Source DMA0_CH4_INT from ADMA Sub-System*/
	.long   ADMA_DMA0_CH5_INT_IRQHandler                    /* Shared Int Source DMA0_CH5_INT from ADMA Sub-System*/
	.long   ADMA_ASRC1_INT1_IRQHandler                      /* Shared Int Source ASRC1_INT1 from ADMA Sub-System*/
	.long   ADMA_ASRC1_INT2_IRQHandler                      /* Shared Int Source ASRC1_INT2 from ADMA Sub-System*/
	.long   ADMA_DMA1_CH0_INT_IRQHandler                    /* Shared Int Source DMA1_CH0_INT from ADMA Sub-System*/
	.long   ADMA_DMA1_CH1_INT_IRQHandler                    /* Shared Int Source DMA1_CH1_INT from ADMA Sub-System*/
	.long   ADMA_DMA1_CH2_INT_IRQHandler                    /* Shared Int Source DMA1_CH2_INT from ADMA Sub-System*/
	.long   ADMA_DMA1_CH3_INT_IRQHandler                    /* Shared Int Source DMA1_CH3_INT from ADMA Sub-System*/
	.long   ADMA_DMA1_CH4_INT_IRQHandler                    /* Shared Int Source DMA1_CH4_INT from ADMA Sub-System*/
	.long   ADMA_DMA1_CH5_INT_IRQHandler                    /* Shared Int Source DMA1_CH5_INT from ADMA Sub-System*/
	.long   ADMA_ESAI0_INT_IRQHandler                       /* Shared Int Source ESAI0_INT from ADMA Sub-System*/
	.long   Reserved488_IRQHandler                          /* xxx Interrupt 488*/
	.long   Reserved489_IRQHandler                          /* xxx Interrupt 489*/
	.long   ADMA_GPT0_INT_IRQHandler                        /* Shared Int Source GPT0_INT from ADMA Sub-System*/
	.long   ADMA_GPT1_INT_IRQHandler                        /* Shared Int Source GPT1_INT from ADMA Sub-System*/
	.long   ADMA_GPT2_INT_IRQHandler                        /* Shared Int Source GPT2_INT from ADMA Sub-System*/
	.long   ADMA_GPT3_INT_IRQHandler                        /* Shared Int Source GPT3_INT from ADMA Sub-System*/
	.long   ADMA_GPT4_INT_IRQHandler                        /* Shared Int Source GPT4_INT from ADMA Sub-System*/
	.long   ADMA_GPT5_INT_IRQHandler                        /* Shared Int Source GPT5_INT from ADMA Sub-System*/
	.long   ADMA_SAI0_INT_IRQHandler                        /* Shared Int Source SAI0_INT from ADMA Sub-System*/
	.long   ADMA_SAI1_INT_IRQHandler                        /* Shared Int Source SAI1_INT from ADMA Sub-System*/
	.long   ADMA_SAI2_INT_IRQHandler                        /* Shared Int Source SAI2_INT from ADMA Sub-System*/
	.long   ADMA_SAI3_INT_IRQHandler                        /* Shared Int Source SAI3_INT from ADMA Sub-System*/
	.long   Reserved500_IRQHandler                          /* xxx Interrupt 500*/
	.long   Reserved501_IRQHandler                          /* xxx Interrupt 501*/
	.long   ADMA_SAI4_INT_IRQHandler                        /* Shared Int Source SAI4_INT from ADMA Sub-System*/
	.long   ADMA_SAI5_INT_IRQHandler                        /* Shared Int Source SAI5_INT from ADMA Sub-System*/
	.long   ADMA_SPDIF0_RX_INT_IRQHandler                   /* Shared Int Source SPDIF0_RX_INT from ADMA Sub-System*/
	.long   ADMA_SPDIF0_TX_INT_IRQHandler                   /* Shared Int Source SPDIF0_TX_INT from ADMA Sub-System*/
	.long   Reserved506_IRQHandler                          /* xxx Interrupt 506*/
	.long   Reserved507_IRQHandler                          /* xxx Interrupt 507*/
	.long   ADMA_ESAI0_MOD_INT_IRQHandler                   /* Shared Int Source ESAI0_MOD_INT from ADMA Sub-System*/
	.long   ADMA_ESAI0_DMA_INT_IRQHandler                   /* Shared Int Source ESAI0_DMA_INT from ADMA Sub-System*/
	.long   Reserved510_IRQHandler                          /* xxx Interrupt 510*/
	.long   Reserved511_IRQHandler                          /* xxx Interrupt 511*/
	.long   Reserved512_IRQHandler                          /* xxx Interrupt 512*/
	.long   Reserved513_IRQHandler                          /* xxx Interrupt 513*/
	.long   Reserved514_IRQHandler                          /* xxx Interrupt 514*/
	.long   ADMA_SPI0_DMA_RX_INT_IRQHandler                 /* Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_SPI0_DMA_TX_INT_IRQHandler                 /* Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_SPI1_DMA_RX_INT_IRQHandler                 /* Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_SPI1_DMA_TX_INT_IRQHandler                 /* Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_SPI2_DMA_RX_INT_IRQHandler                 /* Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_SPI2_DMA_TX_INT_IRQHandler                 /* Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_SPI3_DMA_RX_INT_IRQHandler                 /* Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_SPI3_DMA_TX_INT_IRQHandler                 /* Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_I2C0_DMA_RX_INT_IRQHandler                 /* Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_I2C0_DMA_TX_INT_IRQHandler                 /* Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_I2C1_DMA_RX_INT_IRQHandler                 /* Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_I2C1_DMA_TX_INT_IRQHandler                 /* Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_I2C2_DMA_RX_INT_IRQHandler                 /* Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_I2C2_DMA_TX_INT_IRQHandler                 /* Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_I2C3_DMA_RX_INT_IRQHandler                 /* Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_I2C3_DMA_TX_INT_IRQHandler                 /* Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System*/
	.long   Reserved531_IRQHandler                          /* xxx Interrupt 531*/
	.long   Reserved532_IRQHandler                          /* xxx Interrupt 532*/
	.long   ADMA_UART0_DMA_RX_INT_IRQHandler                /* Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_UART0_DMA_TX_INT_IRQHandler                /* Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_UART1_DMA_RX_INT_IRQHandler                /* Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_UART1_DMA_TX_INT_IRQHandler                /* Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_UART2_DMA_RX_INT_IRQHandler                /* Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_UART2_DMA_TX_INT_IRQHandler                /* Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System*/
	.long   ADMA_UART3_DMA_RX_INT_IRQHandler                /* Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System*/
	.long   ADMA_UART3_DMA_TX_INT_IRQHandler                /* Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System*/
	.long   Reserved541_IRQHandler                          /* xxx Interrupt 541*/
	.long   Reserved542_IRQHandler                          /* xxx Interrupt 542*/
	.long   Reserved543_IRQHandler                          /* xxx Interrupt 543*/
	.long   Reserved544_IRQHandler                          /* xxx Interrupt 544*/
	.long   Reserved545_IRQHandler                          /* xxx Interrupt 545*/
	.long   Reserved546_IRQHandler                          /* xxx Interrupt 546*/
	.long   SECURITY_MU1_A_INT_IRQHandler                   /* Shared Int Source MU1_A_INT from Security Sub-System*/
	.long   SECURITY_MU2_A_INT_IRQHandler                   /* Shared Int Source MU2_A_INT from Security Sub-System*/
	.long   SECURITY_MU3_A_INT_IRQHandler                   /* Shared Int Source MU3_A_INT from Security Sub-System*/
	.long   SECURITY_CAAM_INT0_IRQHandler                   /* Shared Int Source CAAM_INT0 from Security Sub-System*/
	.long   SECURITY_CAAM_INT1_IRQHandler                   /* Shared Int Source CAAM_INT1 from Security Sub-System*/
	.long   SECURITY_CAAM_INT2_IRQHandler                   /* Shared Int Source CAAM_INT2 from Security Sub-System*/
	.long   SECURITY_CAAM_INT3_IRQHandler                   /* Shared Int Source CAAM_INT3 from Security Sub-System*/
	.long   SECURITY_CAAM_RTIC_INT_IRQHandler               /* Shared Int Source CAAM_RTIC_INT from Security Sub-System*/
	.long   ADMA_SPDIF0_RX_MOD_INT_IRQHandler               /* Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SPDIF0_RX_DMA_INT_IRQHandler               /* Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System*/
	.long   ADMA_SPDIF0_TX_MOD_INT_IRQHandler               /* Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System*/
	.long   ADMA_SPDIF0_TX_DMA_INT_IRQHandler               /* Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System*/
	.long   Reserved559_IRQHandler                          /* xxx Interrupt 559*/
	.long   Reserved560_IRQHandler                          /* xxx Interrupt 560*/
	.long   Reserved561_IRQHandler                          /* xxx Interrupt 561*/
	.long   Reserved562_IRQHandler                          /* xxx Interrupt 562*/
	.long   VPU_VPU_INT_0_IRQHandler                        /* Shared Int Source VPU_INT_0 from VPU Sub-System*/
	.long   VPU_VPU_INT_1_IRQHandler                        /* Shared Int Source VPU_INT_1 from VPU Sub-System*/
	.long   VPU_VPU_INT_2_IRQHandler                        /* Shared Int Source VPU_INT_2 from VPU Sub-System*/
	.long   VPU_VPU_INT_3_IRQHandler                        /* Shared Int Source VPU_INT_3 from VPU Sub-System*/
	.long   VPU_VPU_INT_4_IRQHandler                        /* Shared Int Source VPU_INT_4 from VPU Sub-System*/
	.long   Reserved568_IRQHandler                          /* xxx Interrupt 568*/
	.long   Reserved569_IRQHandler                          /* xxx Interrupt 569*/
	.long   Reserved570_IRQHandler                          /* xxx Interrupt 570*/
	.long   Reserved571_IRQHandler                          /* xxx Interrupt 571*/
	.long   Reserved572_IRQHandler                          /* xxx Interrupt 572*/
	.long   Reserved573_IRQHandler                          /* xxx Interrupt 573*/
	.long   Reserved574_IRQHandler                          /* xxx Interrupt 574*/
	.long   Reserved575_IRQHandler                          /* xxx Interrupt 575*/
	.long   Reserved576_IRQHandler                          /* xxx Interrupt 576*/
	.long   Reserved577_IRQHandler                          /* xxx Interrupt 577*/
	.long   Reserved578_IRQHandler                          /* xxx Interrupt 578*/
	.long   Reserved579_IRQHandler                          /* xxx Interrupt 579*/
	.long   M4_INTMUX_SOURCE_TPM_IRQHandler                 /* INTMUX Input source: TPM Interrupt*/
	.long   Reserved581_IRQHandler                          /* xxx Interrupt 581*/
	.long   Reserved582_IRQHandler                          /* xxx Interrupt 582*/
	.long   M4_INTMUX_SOURCE_LPIT_IRQHandler                /* INTMUX Input source: LPIT Interrupt*/
	.long   Reserved584_IRQHandler                          /* xxx Interrupt 584*/
	.long   Reserved585_IRQHandler                          /* xxx Interrupt 585*/
	.long   M4_INTMUX_SOURCE_LPUART_IRQHandler              /* INTMUX Input source: LPUART Interrupt*/
	.long   Reserved587_IRQHandler                          /* xxx Interrupt 587*/
	.long   M4_INTMUX_SOURCE_LPI2C_IRQHandler               /* INTMUX Input source: LPI2C Interrupt*/
	.long   Reserved589_IRQHandler                          /* xxx Interrupt 589*/
	.long   Reserved590_IRQHandler                          /* xxx Interrupt 590*/
	.long   Reserved591_IRQHandler                          /* xxx Interrupt 591*/
	.long   Reserved592_IRQHandler                          /* xxx Interrupt 592*/
	.long   Reserved593_IRQHandler                          /* xxx Interrupt 593*/
	.long   Reserved594_IRQHandler                          /* xxx Interrupt 594*/
	.long   Reserved595_IRQHandler                          /* xxx Interrupt 595*/
	.long   Reserved596_IRQHandler                          /* xxx Interrupt 596*/
	.long   Reserved597_IRQHandler                          /* xxx Interrupt 597*/
	.long   Reserved598_IRQHandler                          /* xxx Interrupt 598*/
	.long   Reserved599_IRQHandler                          /* xxx Interrupt 599*/
	.long   Reserved600_IRQHandler                          /* xxx Interrupt 600*/
	.long   Reserved601_IRQHandler                          /* xxx Interrupt 601*/
	.long   Reserved602_IRQHandler                          /* xxx Interrupt 602*/
	.long   Reserved603_IRQHandler                          /* xxx Interrupt 603*/
	.long   Reserved604_IRQHandler                          /* xxx Interrupt 604*/
	.long   Reserved605_IRQHandler                          /* xxx Interrupt 605*/
	.long   Reserved606_IRQHandler                          /* xxx Interrupt 606*/
	.long   M4_INTMUX_SOURCE_MU0_A3_IRQHandler              /* INTMUX Input source: MU0_A3 Interrupt*/
	.long   M4_INTMUX_SOURCE_MU0_A2_IRQHandler              /* INTMUX Input source: MU0_A2 Interrupt*/
	.long   M4_INTMUX_SOURCE_MU0_A1_IRQHandler              /* INTMUX Input source: MU0_A1 Interrupt*/
	.long   M4_INTMUX_SOURCE_MU0_A0_IRQHandler              /* INTMUX Input source: MU0_A0 Interrupt*/
	.long   DefaultISR                                      /* 611*/
	.long   DefaultISR                                      /* 612*/
	.long   DefaultISR                                      /* 613*/
	.long   DefaultISR                                      /* 614*/
	.long   DefaultISR                                      /* 615*/
	.long   DefaultISR                                      /* 616*/
	.long   DefaultISR                                      /* 617*/
	.long   DefaultISR                                      /* 618*/
	.long   DefaultISR                                      /* 619*/
	.long   DefaultISR                                      /* 620*/
	.long   DefaultISR                                      /* 621*/
	.long   DefaultISR                                      /* 622*/
	.long   DefaultISR                                      /* 623*/
	.long   DefaultISR                                      /* 624*/
	.long   DefaultISR                                      /* 625*/
	.long   DefaultISR                                      /* 626*/
	.long   DefaultISR                                      /* 627*/
	.long   DefaultISR                                      /* 628*/
	.long   DefaultISR                                      /* 629*/
	.long   DefaultISR                                      /* 630*/
	.long   DefaultISR                                      /* 631*/
	.long   DefaultISR                                      /* 632*/
	.long   DefaultISR                                      /* 633*/
	.long   DefaultISR                                      /* 634*/
	.long   DefaultISR                                      /* 635*/
	.long   DefaultISR                                      /* 636*/
	.long   DefaultISR                                      /* 637*/
	.long   DefaultISR                                      /* 638*/
	.long   DefaultISR                                      /* 639*/

	.size    __isr_vector, . - __isr_vector

	.text
	.thumb

/* Reset Handler */

	.thumb_func
	.align 2
	.globl   Reset_Handler
	.weak    Reset_Handler
	.type    Reset_Handler, %function
Reset_Handler:
	cpsid   i               /* Mask interrupts */
	.equ    VTOR, 0xE000ED08
	ldr     r0, =VTOR
	ldr     r1, =__isr_vector
	str     r1, [r0]
	ldr     r2, [r1]
	msr     msp, r2
#ifndef __NO_SYSTEM_INIT
	ldr   r0,=SystemInit
	blx   r0
#endif
/*     Loop to copy data from read only memory to RAM. The ranges
 *      of copy from/to are specified by following symbols evaluated in
 *      linker script.
 *      __etext: End of code section, i.e., begin of data sections to copy from.
 *      __data_start__/__data_end__: RAM address range that data should be
 *      __noncachedata_start__/__noncachedata_end__ : none cachable region
 *      copied to. Both must be aligned to 4 bytes boundary.  */

	ldr    r1, =__etext
	ldr    r2, =__data_start__
	ldr    r3, =__data_end__

#if 1
/* Here are two copies of loop implemenations. First one favors code size
 * and the second one favors performance. Default uses the first one.
 * Change to "#if 0" to use the second one */
.LC0:
	cmp     r2, r3
	ittt    lt
	ldrlt   r0, [r1], #4
	strlt   r0, [r2], #4
	blt    .LC0
#else
	subs    r3, r2
	ble    .LC1
.LC0:
	subs    r3, #4
	ldr    r0, [r1, r3]
	str    r0, [r2, r3]
	bgt    .LC0
.LC1:
#endif

/*     Loop to copy data from read only memory to RAM. The ranges
 *      of copy from/to are specified by following symbols evaluated in
 *      linker script.
 *      __quickaccess_start__/__quickaccess_end__: RAM address range that data should be
 *      copied to. Both must be aligned to 4 bytes boundary.  */
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
	ldr    r2, = __quickaccess_start__
	ldr    r3, = __quickaccess_end__
#if 1
.LC2:
	cmp     r2, r3
	ittt    lt
	ldrlt   r0, [r1], #4
	strlt   r0, [r2], #4
	blt    .LC2
#else
	subs    r3, r2
	ble    .LC3
.LC2:
	subs    r3, #4
	ldr     r0, [r1, r3]
	str     r0, [r2, r3]
	bgt    .LC2
.LC3:
#endif
#endif /* FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */

/*      __resume_mem_start__/__resume_mem_end__: DDR address range that data should be
 *      retained during LPM. Both must be aligned to 4 bytes boundary.  */
#ifdef __STARTUP_INITIALIZE_RESUMEMEM
	ldr    r1, = __RDATA_ROM
	ldr    r2, = __resume_mem_start__
	ldr    r3, = __resume_mem_end__
#if 1
.LC4:
	cmp     r2, r3
	ittt    lt
	ldrlt   r0, [r1], #4
	strlt   r0, [r2], #4
	blt    .LC4
#else
	subs    r3, r2
	ble    .LC5
.LC4:
	subs    r3, #4
	ldr     r0, [r1, r3]
	str     r0, [r2, r3]
	bgt    .LC4
.LC5:
#endif
#endif /* __STARTUP_INITIALIZE_RESUMEMEM */

#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
	ldr    r1, =__NDATA_ROM
	ldr    r2, =__noncachedata_start__
	ldr    r3, =__noncachedata_init_end__
#if 1
.LC6:
	cmp     r2, r3
	ittt    lt
	ldrlt   r0, [r1], #4
	strlt   r0, [r2], #4
	blt    .LC6
#else
	subs    r3, r2
	ble    .LC7
.LC6:
	subs    r3, #4
	ldr     r0, [r1, r3]
	str     r0, [r2, r3]
	bgt    .LC6
.LC7:
#endif
/* Add ncache section initializaiton */
	ldr r3, =__noncachedata_end__
	movs    r0, 0
.LC8:
	cmp     r2, r3
	itt    lt
	strlt   r0, [r2], #4
	blt    .LC8
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */

#ifdef __STARTUP_CLEAR_BSS
/*     This part of work usually is done in C library startup code. Otherwise,
 *     define this macro to enable it in this startup.
 *
 *     Loop to zero out BSS section, which uses following symbols
 *     in linker script:
 *      __bss_start__: start of BSS section. Must align to 4
 *      __bss_end__: end of BSS section. Must align to 4
 */
	ldr r1, =__bss_start__
	ldr r2, =__bss_end__

	movs    r0, 0
.LC9:
	cmp     r1, r2
	itt    lt
	strlt   r0, [r1], #4
	blt    .LC9
#endif /* __STARTUP_CLEAR_BSS */

/* Add stack / heap initializaiton */
	movs    r0, 0
	ldr     r1, =__HeapBase
	ldr     r2, =__HeapLimit
.LC10:
	cmp     r1, r2
	itt     lt
	strlt   r0, [r1], #4
	blt     .LC10

	ldr     r1, =__StackLimit
	ldr     r2, =__StackTop
.LC11:
	cmp     r1, r2
	itt     lt
	strlt   r0, [r1], #4
	blt     .LC11

/*End of stack / heap initializaiton */
	cpsie   i               /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
	ldr   r0,=__START
	blx   r0
#else
	ldr   r0,=__libc_init_array
	blx   r0
	ldr   r0,=main
	bx    r0
#endif
	.pool
	.size Reset_Handler, . - Reset_Handler

	.align  1
	.thumb_func
	.weak DefaultISR
	.type DefaultISR, %function
DefaultISR:
	b DefaultISR
	.size DefaultISR, . - DefaultISR

	.align 1
	.thumb_func
	.weak NMI_Handler
	.type NMI_Handler, %function
NMI_Handler:
	ldr   r0,=NMI_Handler
	bx    r0
	.size NMI_Handler, . - NMI_Handler

	.align 1
	.thumb_func
	.weak HardFault_Handler
	.type HardFault_Handler, %function
HardFault_Handler:
	ldr   r0,=HardFault_Handler
	bx    r0
	.size HardFault_Handler, . - HardFault_Handler

	.align 1
	.thumb_func
	.weak SVC_Handler
	.type SVC_Handler, %function
SVC_Handler:
	ldr   r0,=SVC_Handler
	bx    r0
	.size SVC_Handler, . - SVC_Handler

	.align 1
	.thumb_func
	.weak PendSV_Handler
	.type PendSV_Handler, %function
PendSV_Handler:
	ldr   r0,=PendSV_Handler
	bx    r0
	.size PendSV_Handler, . - PendSV_Handler

	.align 1
	.thumb_func
	.weak SysTick_Handler
	.type SysTick_Handler, %function
SysTick_Handler:
	ldr   r0,=SysTick_Handler
	bx    r0
	.size SysTick_Handler, . - SysTick_Handler

	.align 1
	.thumb_func
	.weak M4_LPUART_IRQHandler
	.type M4_LPUART_IRQHandler, %function
M4_LPUART_IRQHandler:
	ldr   r0,=M4_LPUART_DriverIRQHandler
	bx    r0
	.size M4_LPUART_IRQHandler, . - M4_LPUART_IRQHandler

	.align 1
	.thumb_func
	.weak M4_LPI2C_IRQHandler
	.type M4_LPI2C_IRQHandler, %function
M4_LPI2C_IRQHandler:
	ldr   r0,=M4_LPI2C_DriverIRQHandler
	bx    r0
	.size M4_LPI2C_IRQHandler, . - M4_LPI2C_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_0_IRQHandler
	.type IRQSTEER_0_IRQHandler, %function
IRQSTEER_0_IRQHandler:
	ldr   r0,=IRQSTEER_0_DriverIRQHandler
	bx    r0
	.size IRQSTEER_0_IRQHandler, . - IRQSTEER_0_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_1_IRQHandler
	.type IRQSTEER_1_IRQHandler, %function
IRQSTEER_1_IRQHandler:
	ldr   r0,=IRQSTEER_1_DriverIRQHandler
	bx    r0
	.size IRQSTEER_1_IRQHandler, . - IRQSTEER_1_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_2_IRQHandler
	.type IRQSTEER_2_IRQHandler, %function
IRQSTEER_2_IRQHandler:
	ldr   r0,=IRQSTEER_2_DriverIRQHandler
	bx    r0
	.size IRQSTEER_2_IRQHandler, . - IRQSTEER_2_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_3_IRQHandler
	.type IRQSTEER_3_IRQHandler, %function
IRQSTEER_3_IRQHandler:
	ldr   r0,=IRQSTEER_3_DriverIRQHandler
	bx    r0
	.size IRQSTEER_3_IRQHandler, . - IRQSTEER_3_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_4_IRQHandler
	.type IRQSTEER_4_IRQHandler, %function
IRQSTEER_4_IRQHandler:
	ldr   r0,=IRQSTEER_4_DriverIRQHandler
	bx    r0
	.size IRQSTEER_4_IRQHandler, . - IRQSTEER_4_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_5_IRQHandler
	.type IRQSTEER_5_IRQHandler, %function
IRQSTEER_5_IRQHandler:
	ldr   r0,=IRQSTEER_5_DriverIRQHandler
	bx    r0
	.size IRQSTEER_5_IRQHandler, . - IRQSTEER_5_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_6_IRQHandler
	.type IRQSTEER_6_IRQHandler, %function
IRQSTEER_6_IRQHandler:
	ldr   r0,=IRQSTEER_6_DriverIRQHandler
	bx    r0
	.size IRQSTEER_6_IRQHandler, . - IRQSTEER_6_IRQHandler

	.align 1
	.thumb_func
	.weak IRQSTEER_7_IRQHandler
	.type IRQSTEER_7_IRQHandler, %function
IRQSTEER_7_IRQHandler:
	ldr   r0,=IRQSTEER_7_DriverIRQHandler
	bx    r0
	.size IRQSTEER_7_IRQHandler, . - IRQSTEER_7_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EDMA2_INT_IRQHandler
	.type ADMA_EDMA2_INT_IRQHandler, %function
ADMA_EDMA2_INT_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EDMA2_INT_IRQHandler, . - ADMA_EDMA2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EDMA2_ERR_INT_IRQHandler
	.type ADMA_EDMA2_ERR_INT_IRQHandler, %function
ADMA_EDMA2_ERR_INT_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EDMA2_ERR_INT_IRQHandler, . - ADMA_EDMA2_ERR_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EDMA3_INT_IRQHandler
	.type ADMA_EDMA3_INT_IRQHandler, %function
ADMA_EDMA3_INT_IRQHandler:
	ldr   r0,=ADMA_EDMA3_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EDMA3_INT_IRQHandler, . - ADMA_EDMA3_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EDMA3_ERR_INT_IRQHandler
	.type ADMA_EDMA3_ERR_INT_IRQHandler, %function
ADMA_EDMA3_ERR_INT_IRQHandler:
	ldr   r0,=ADMA_EDMA3_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EDMA3_ERR_INT_IRQHandler, . - ADMA_EDMA3_ERR_INT_IRQHandler

	.align 1
	.thumb_func
	.weak LSIO_OCTASPI0_INT_IRQHandler
	.type LSIO_OCTASPI0_INT_IRQHandler, %function
LSIO_OCTASPI0_INT_IRQHandler:
	ldr   r0,=LSIO_OCTASPI0_INT_DriverIRQHandler
	bx    r0
	.size LSIO_OCTASPI0_INT_IRQHandler, . - LSIO_OCTASPI0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak LSIO_OCTASPI1_INT_IRQHandler
	.type LSIO_OCTASPI1_INT_IRQHandler, %function
LSIO_OCTASPI1_INT_IRQHandler:
	ldr   r0,=LSIO_OCTASPI1_INT_DriverIRQHandler
	bx    r0
	.size LSIO_OCTASPI1_INT_IRQHandler, . - LSIO_OCTASPI1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak HSIO_PCIEB_DMA_INT_IRQHandler
	.type HSIO_PCIEB_DMA_INT_IRQHandler, %function
HSIO_PCIEB_DMA_INT_IRQHandler:
	ldr   r0,=HSIO_PCIEB_DMA_INT_DriverIRQHandler
	bx    r0
	.size HSIO_PCIEB_DMA_INT_IRQHandler, . - HSIO_PCIEB_DMA_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_SPI0_INT_IRQHandler
	.type ADMA_SPI0_INT_IRQHandler, %function
ADMA_SPI0_INT_IRQHandler:
	ldr   r0,=ADMA_SPI0_INT_DriverIRQHandler
	bx    r0
	.size ADMA_SPI0_INT_IRQHandler, . - ADMA_SPI0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_SPI1_INT_IRQHandler
	.type ADMA_SPI1_INT_IRQHandler, %function
ADMA_SPI1_INT_IRQHandler:
	ldr   r0,=ADMA_SPI1_INT_DriverIRQHandler
	bx    r0
	.size ADMA_SPI1_INT_IRQHandler, . - ADMA_SPI1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_SPI2_INT_IRQHandler
	.type ADMA_SPI2_INT_IRQHandler, %function
ADMA_SPI2_INT_IRQHandler:
	ldr   r0,=ADMA_SPI2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_SPI2_INT_IRQHandler, . - ADMA_SPI2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_SPI3_INT_IRQHandler
	.type ADMA_SPI3_INT_IRQHandler, %function
ADMA_SPI3_INT_IRQHandler:
	ldr   r0,=ADMA_SPI3_INT_DriverIRQHandler
	bx    r0
	.size ADMA_SPI3_INT_IRQHandler, . - ADMA_SPI3_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_I2C0_INT_IRQHandler
	.type ADMA_I2C0_INT_IRQHandler, %function
ADMA_I2C0_INT_IRQHandler:
	ldr   r0,=ADMA_I2C0_INT_DriverIRQHandler
	bx    r0
	.size ADMA_I2C0_INT_IRQHandler, . - ADMA_I2C0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_I2C1_INT_IRQHandler
	.type ADMA_I2C1_INT_IRQHandler, %function
ADMA_I2C1_INT_IRQHandler:
	ldr   r0,=ADMA_I2C1_INT_DriverIRQHandler
	bx    r0
	.size ADMA_I2C1_INT_IRQHandler, . - ADMA_I2C1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_I2C2_INT_IRQHandler
	.type ADMA_I2C2_INT_IRQHandler, %function
ADMA_I2C2_INT_IRQHandler:
	ldr   r0,=ADMA_I2C2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_I2C2_INT_IRQHandler, . - ADMA_I2C2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_I2C3_INT_IRQHandler
	.type ADMA_I2C3_INT_IRQHandler, %function
ADMA_I2C3_INT_IRQHandler:
	ldr   r0,=ADMA_I2C3_INT_DriverIRQHandler
	bx    r0
	.size ADMA_I2C3_INT_IRQHandler, . - ADMA_I2C3_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_I2C4_INT_IRQHandler
	.type ADMA_I2C4_INT_IRQHandler, %function
ADMA_I2C4_INT_IRQHandler:
	ldr   r0,=ADMA_I2C4_INT_DriverIRQHandler
	bx    r0
	.size ADMA_I2C4_INT_IRQHandler, . - ADMA_I2C4_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_UART0_INT_IRQHandler
	.type ADMA_UART0_INT_IRQHandler, %function
ADMA_UART0_INT_IRQHandler:
	ldr   r0,=ADMA_UART0_INT_DriverIRQHandler
	bx    r0
	.size ADMA_UART0_INT_IRQHandler, . - ADMA_UART0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_UART1_INT_IRQHandler
	.type ADMA_UART1_INT_IRQHandler, %function
ADMA_UART1_INT_IRQHandler:
	ldr   r0,=ADMA_UART1_INT_DriverIRQHandler
	bx    r0
	.size ADMA_UART1_INT_IRQHandler, . - ADMA_UART1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_UART2_INT_IRQHandler
	.type ADMA_UART2_INT_IRQHandler, %function
ADMA_UART2_INT_IRQHandler:
	ldr   r0,=ADMA_UART2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_UART2_INT_IRQHandler, . - ADMA_UART2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_UART3_INT_IRQHandler
	.type ADMA_UART3_INT_IRQHandler, %function
ADMA_UART3_INT_IRQHandler:
	ldr   r0,=ADMA_UART3_INT_DriverIRQHandler
	bx    r0
	.size ADMA_UART3_INT_IRQHandler, . - ADMA_UART3_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_USDHC0_INT_IRQHandler
	.type CONNECTIVITY_USDHC0_INT_IRQHandler, %function
CONNECTIVITY_USDHC0_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_USDHC0_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_USDHC0_INT_IRQHandler, . - CONNECTIVITY_USDHC0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_USDHC1_INT_IRQHandler
	.type CONNECTIVITY_USDHC1_INT_IRQHandler, %function
CONNECTIVITY_USDHC1_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_USDHC1_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_USDHC1_INT_IRQHandler, . - CONNECTIVITY_USDHC1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_USDHC2_INT_IRQHandler
	.type CONNECTIVITY_USDHC2_INT_IRQHandler, %function
CONNECTIVITY_USDHC2_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_USDHC2_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_USDHC2_INT_IRQHandler, . - CONNECTIVITY_USDHC2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_FLEXCAN0_INT_IRQHandler
	.type ADMA_FLEXCAN0_INT_IRQHandler, %function
ADMA_FLEXCAN0_INT_IRQHandler:
	ldr   r0,=ADMA_FLEXCAN0_INT_DriverIRQHandler
	bx    r0
	.size ADMA_FLEXCAN0_INT_IRQHandler, . - ADMA_FLEXCAN0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_FLEXCAN1_INT_IRQHandler
	.type ADMA_FLEXCAN1_INT_IRQHandler, %function
ADMA_FLEXCAN1_INT_IRQHandler:
	ldr   r0,=ADMA_FLEXCAN1_INT_DriverIRQHandler
	bx    r0
	.size ADMA_FLEXCAN1_INT_IRQHandler, . - ADMA_FLEXCAN1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_FLEXCAN2_INT_IRQHandler
	.type ADMA_FLEXCAN2_INT_IRQHandler, %function
ADMA_FLEXCAN2_INT_IRQHandler:
	ldr   r0,=ADMA_FLEXCAN2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_FLEXCAN2_INT_IRQHandler, . - ADMA_FLEXCAN2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_FTM0_INT_IRQHandler
	.type ADMA_FTM0_INT_IRQHandler, %function
ADMA_FTM0_INT_IRQHandler:
	ldr   r0,=ADMA_FTM0_INT_DriverIRQHandler
	bx    r0
	.size ADMA_FTM0_INT_IRQHandler, . - ADMA_FTM0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_FTM1_INT_IRQHandler
	.type ADMA_FTM1_INT_IRQHandler, %function
ADMA_FTM1_INT_IRQHandler:
	ldr   r0,=ADMA_FTM1_INT_DriverIRQHandler
	bx    r0
	.size ADMA_FTM1_INT_IRQHandler, . - ADMA_FTM1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_ADC0_INT_IRQHandler
	.type ADMA_ADC0_INT_IRQHandler, %function
ADMA_ADC0_INT_IRQHandler:
	ldr   r0,=ADMA_ADC0_INT_DriverIRQHandler
	bx    r0
	.size ADMA_ADC0_INT_IRQHandler, . - ADMA_ADC0_INT_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EXTERNAL_DMA_INT_0_IRQHandler
	.type ADMA_EXTERNAL_DMA_INT_0_IRQHandler, %function
ADMA_EXTERNAL_DMA_INT_0_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EXTERNAL_DMA_INT_0_IRQHandler, . - ADMA_EXTERNAL_DMA_INT_0_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EXTERNAL_DMA_INT_1_IRQHandler
	.type ADMA_EXTERNAL_DMA_INT_1_IRQHandler, %function
ADMA_EXTERNAL_DMA_INT_1_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EXTERNAL_DMA_INT_1_IRQHandler, . - ADMA_EXTERNAL_DMA_INT_1_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EXTERNAL_DMA_INT_2_IRQHandler
	.type ADMA_EXTERNAL_DMA_INT_2_IRQHandler, %function
ADMA_EXTERNAL_DMA_INT_2_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EXTERNAL_DMA_INT_2_IRQHandler, . - ADMA_EXTERNAL_DMA_INT_2_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EXTERNAL_DMA_INT_3_IRQHandler
	.type ADMA_EXTERNAL_DMA_INT_3_IRQHandler, %function
ADMA_EXTERNAL_DMA_INT_3_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EXTERNAL_DMA_INT_3_IRQHandler, . - ADMA_EXTERNAL_DMA_INT_3_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EXTERNAL_DMA_INT_4_IRQHandler
	.type ADMA_EXTERNAL_DMA_INT_4_IRQHandler, %function
ADMA_EXTERNAL_DMA_INT_4_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EXTERNAL_DMA_INT_4_IRQHandler, . - ADMA_EXTERNAL_DMA_INT_4_IRQHandler

	.align 1
	.thumb_func
	.weak ADMA_EXTERNAL_DMA_INT_5_IRQHandler
	.type ADMA_EXTERNAL_DMA_INT_5_IRQHandler, %function
ADMA_EXTERNAL_DMA_INT_5_IRQHandler:
	ldr   r0,=ADMA_EDMA2_INT_DriverIRQHandler
	bx    r0
	.size ADMA_EXTERNAL_DMA_INT_5_IRQHandler, . - ADMA_EXTERNAL_DMA_INT_5_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET0_FRAME1_INT_IRQHandler
	.type CONNECTIVITY_ENET0_FRAME1_INT_IRQHandler, %function
CONNECTIVITY_ENET0_FRAME1_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET0_FRAME1_INT_IRQHandler, . - CONNECTIVITY_ENET0_FRAME1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET0_FRAME2_INT_IRQHandler
	.type CONNECTIVITY_ENET0_FRAME2_INT_IRQHandler, %function
CONNECTIVITY_ENET0_FRAME2_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET0_FRAME2_INT_IRQHandler, . - CONNECTIVITY_ENET0_FRAME2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQHandler
	.type CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQHandler, %function
CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQHandler, . - CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET0_TIMER_INT_IRQHandler
	.type CONNECTIVITY_ENET0_TIMER_INT_IRQHandler, %function
CONNECTIVITY_ENET0_TIMER_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET0_TIMER_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET0_TIMER_INT_IRQHandler, . - CONNECTIVITY_ENET0_TIMER_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET1_FRAME1_INT_IRQHandler
	.type CONNECTIVITY_ENET1_FRAME1_INT_IRQHandler, %function
CONNECTIVITY_ENET1_FRAME1_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET1_FRAME1_INT_IRQHandler, . - CONNECTIVITY_ENET1_FRAME1_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET1_FRAME2_INT_IRQHandler
	.type CONNECTIVITY_ENET1_FRAME2_INT_IRQHandler, %function
CONNECTIVITY_ENET1_FRAME2_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET1_FRAME2_INT_IRQHandler, . - CONNECTIVITY_ENET1_FRAME2_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQHandler
	.type CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQHandler, %function
CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQHandler, . - CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_ENET1_TIMER_INT_IRQHandler
	.type CONNECTIVITY_ENET1_TIMER_INT_IRQHandler, %function
CONNECTIVITY_ENET1_TIMER_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_ENET1_TIMER_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_ENET1_TIMER_INT_IRQHandler, . - CONNECTIVITY_ENET1_TIMER_INT_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_APBHDMA_IRQHandler
	.type CONNECTIVITY_APBHDMA_IRQHandler, %function
CONNECTIVITY_APBHDMA_IRQHandler:
	ldr   r0,=CONNECTIVITY_APBHDMA_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_APBHDMA_IRQHandler, . - CONNECTIVITY_APBHDMA_IRQHandler

	.align 1
	.thumb_func
	.weak CONNECTIVITY_DMA_INT_IRQHandler
	.type CONNECTIVITY_DMA_INT_IRQHandler, %function
CONNECTIVITY_DMA_INT_IRQHandler:
	ldr   r0,=CONNECTIVITY_DMA_INT_DriverIRQHandler
	bx    r0
	.size CONNECTIVITY_DMA_INT_IRQHandler, . - CONNECTIVITY_DMA_INT_IRQHandler
19

Nice work. It seems you found something significant.

The assembly language you are referring to is part of C startup code. It is intended to initialize all of your global and static variables that start with nonzero values. (There is typically a second loop to initialize the ones that start with zero.) The loop copies from flash, which holds the initial values, into RAM. The code looks OK, but I cringe at starting the copy from __etext instead of a dedicated start address for the initialization data, especially on a thumb device that supports 16-bit instructions. If your linker file doesn’t align __etext properly, you could end up with a misalignment in these initializations. Point is there must be careful coordination between this code and the linker.

Are you having trouble with the correct initial value of all variables with a nonzero initial value?

20

It may be helpful if you attach your linker script and map file as well.

Thanks.

1 Like
21

@jefftenney no, just the variable SystemCoreClock is incorrect.

Linker Script:
https://github.com/my777ang/Attachment/blob/master/MIMX8QX6xxxxx_cm4_ram.ld

map file:
https://github.com/my777ang/Attachment/blob/master/output.map

Thanks again.

22

Check the map file for where the definition of SystemCoreClock is coming from. Is that the file you were showing us the snippet from?

23

There’s another cringe item here, for me anyway. As a quick experiment, can you put

    . = ALIGN(8);

at line 137 of the linker script, just before __etext gets assigned.